DMA programming errors. STMicroelectronics SPC58xNx 32-bit Power Architecture microcontroller, SPC58NN84C3, SPC58NN84E7
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Enhanced Direct Memory Access (eDMA)
Figure 213. Memory array terms
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23.5.2 DMA programming errors
The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per-channel basis with the exception of two errors: the group priority error (ES[GPE]) and the channel priority error
(ES[CPE]).
For all error types other than group or channel priority errors, the channel number causing the error is recorded in the ES register. If the error source is not removed before the next activation of the problem channel, the error is detected and recorded again.
Channel priority errors are identified within a group once that group has been selected as the active group. For example:
1.
The eDMA is configured for fixed-group and fixed-channel arbitration modes.
2. Group 3 is the highest priority and all channels are unique in that group.
3. Group 2 is the next highest priority and has two channels with the same priority level.
4. If Group 3 has any service requests, those requests will be executed.
5. Once all of Group 3 requests have completed, Group 2 will be the next active group.
6. If Group 2 has a service request, then an undefined channel in Group 2 will be selected and a channel priority error will occur.
7. This repeats until all of the Group 2 requests have been removed or a higher priority
Group 3 request comes in.
In this sequence, for item 2, the eDMA Acknowledge lines will assert only if the selected channel is requesting service via the eDMA peripheral request signal. If interrupts are enabled for all channels, the user will get an error interrupt, but the channel number for the
ERR register and the error interrupt request line may be wrong because they reflect the
RM0421 Rev 5
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