RM0421 GTM344 Integration (GTMINT) Module
Figure 617. Timestamp Update Signal Stretch
45.4 Programming Guidelines
45.4.1 Initialization/Application Information
The GTM integration module receives two active low reset signals, one on the slave bus clock domain, and the other in the peripheral clock domain. The last one resets all the timer logic, and registers inside the GTM-IP block. Just after this reset signal is negated, the
GTM-IP is in the following condition:
• The GTM bridge is in asynchronous mode.
• after reset, write operations waits the response status (write response is not masked).
• If MDIS_DEFAULT is 1, a write access to GTMMCR is necessary to clear the MDIS bit register and have the GTM-IP clocks toggling.
• DPLL RAMs and MCSs RAMs starts the write initialization cycles. This is necessary for
ECC parity bits storage on each RAM address.
• FIFO0 RAM is not automatically initialized. In normal operation mode, the initialization is not required because the FIFO memory always have to written first to be read later.
Refer to GTM-IP and GTMDI documentation to initialize the GTMINT module.
45.4.2 GTM - ADC Interface Programming
While programming the external ADCQ modules and the GTM MCS sub-modules the
system should follow the steps given in Figure 614 .
• First the conversion list should be prepared which contains the list of ADC channels.
• Then this conversion list should be programmed in the external ADCs.
•
After programming the external ADCs software should program External ADC Select
Register to map the MCS interfaces with the external ADCQ modules.
• This mapping of MCS modules with external ADCQ should be done when
MCS_ADC_SEL_EN bit is low. During the first write to this register only bits [19:0]
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GTM344 Integration (GTMINT) Module RM0421 should be programmed and in second write GTM-ADCQ interface can be enabled by writing MCS_ADC_SEL_EN bit as 1.
• Special care should be taken while programming this register so that no two MCS submodules are mapped to the same ADCQ. Hence no two MCS x _ADC_SEL fields can have the same value programmed.
• After writing 1 to MCS_ADC_SEL_EN bit wait for MCS_ADC_EN_ACK bit to go high.
The transactions should be done on MCS-ADC interface only when this
MCS_ADC_EN_ACK bit is high.
• GTM MCS-ADCQ mapping should not be changed during run-time when the GTM-
ADC interface is in operation.
• After this the conversion data should be read by MCS instructions using either normal access or burst access.
• Match the channel numbers from the data read and store the conversion data in internal buffers accordingly.
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