Dual PLL digital interface (PLLDIG) RM0421
Note:
Note:
Note:
Depending on DTHDIS value the multiplication factor of
Equation 8
can change as described in PLL1DV[DTHDIS] field description (refer to
Table 347
).
f pll0_phi1
is the reference clock generated by PLL0 for PLL1.
When programming the PLLs, user software must not violate the maximum system clock frequency or max/min VCO frequency specification for PLL0 or PLL1 (refer to the device datasheet). Furthermore, the PLL0DV[PREDIV] value must not be set to any value that causes the input frequency to the phase detector of analog PLL blocks to go below the prescribed ranges.
The lock signal and PLL n SR[LOCK] flag are immediately negated if the fields of PLL n DV are changed without powering down the analog PLLs.
When any of these events occur, an internal timer is initialized to count 64 cycles of the PLL input clock. During this period (64 cycles and a few extra clock cycles for synchronization, for example, 64 to 72 cycles), the PLL n SR[LOCK] flag is held negated. After the timer expires, the PLL n SR[LOCK] flag reflects the value coming from the PLL lock detection circuitry. To prevent an immediate reset, the PLL n CR[LOLRE] bit of the respective PLLs must be cleared before doing any of the above operations.
The PLL must be powered down and powered up by configuring <ME_mode>_MC before
PLL0CR[PREDIV], PLL0CR[MFD], PLL1CR[MFD] or the input reference clock values are modified.
The recommended procedure to program the PLLs and engage normal mode is shown in
Section 26.7
.
26.6.3 Frequency modulation
Frequency modulation uses a triangular profile as shown in
Figure 239
. The modulation frequency and depth are controlled using PLL1FM[MODPRD] and PLL1FM[INCSTP].
Figure 239. Triangular frequency modulation f pll1_phi
= PLL nominal frequency
MD = Modulation depth percentage f pll1_phi
MD
Center spread
2 x MD Down spread f pll1_phi
Note: The device maximum operating frequency includes the frequency modulation. If center modulation is selected, the fsys must be below fmax by MD percentage such that fmax = fsys(1 + MD%). Refer to the
Analog PLL chapter for more details.
The following equations define how to calculate PLL1FM[MODPRD] ( Equation 9 ) and
PLL1FM[INCSTP] ( Equation 10
) based on the frequency of the feedback divider (f pll1_ref the modulation frequency (f mod
) and the modulation depth percentage (MD):
),
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RM0421 Rev 5
RM0421 Dual PLL digital interface (PLLDIG)
Equation 9
PLL1FM[MODPRD]
=
round
-----------------------
Equation 10
PLL1FM[INCSTP]
=
round
(
2
15
–
100 5
) ×
×
MD
×
×
PLL1FM[MODPRD]
PLL1FM[MODPRD] and PLL1FM[INCSTP] are subject to the following restriction:
Equation 11
( ) <
2
15
Because of the above rounding operations, the effective modulation depth applied to the
FMPLL is given by the following formula:
Equation 12
ModulationDepth = round
-----------------------------------------------------------------------------------------------------------------------------------------------
( 2 – 1 ) × [ ]
] 100 5
As an example, suppose the following configuration:
• Input frequency: 40 MHz
• Loop divider (PLL1DV[MFD]): 20
• Input divider: 1
• Output divider RFD: 5
• VCO frequency: 40 MHz × 20 = 800 MHz
• PLL output frequency: 800 MHz / 2*RFD = 800 MHz / 10 = 80 MHz
• Center spread (PLL1FM[MODSEL] = 0)
• Modulation frequency: 200 kHz
• Modulation depth: ± 1.9% (3.8% peak-to-peak)
• PLL1FM[MODPRD] = Round[(40 × 10 6 ) / (4 × 200 × 10 3 )] = Round[50] = 50
• PLL1FM[INCSTP] = Round[((2
15 − 1) × 1.9× 20) / (100 × 5 × 50)] = Round[49.8] = 50
• PLL1FM[MODPRD] × PLL1FM[INCSTP] = 50 × 50 = 2500 (which is less than 2 15 )
• MD (quantized) = ((50 × 50 × 100 × 5) / ((2
15 − 1) × 20) = 1.90740%
In this example, the modulation error is 0.00740%.
The FM parameters do not get reset when PLL0 looses its lock. These parameters get reset on destructive reset. Whenever PLL0 gets relocked FM modulation starts with the previous values.
The sequence for reprogramming the FM is:
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