Dual PLL digital interface (PLLDIG)
1.
Power down PLL1 (h)
2. Program the PLL1FM while PLL1 is powered down
3. Power up the PLL1 (i)
RM0421
26.7 Initialization information
Coming out of reset the PLLs are disabled per the DRUN mode configuration register
(< ME>_ DRUN_MC). The recommended procedure
(j)
to program the PLLs and enter normal mode is:
1.
Configure PLL0 and related modules.
Program PLL0DV[PREDIV], PLL0DV[RFDPHI1], PLL0DV[MFD] and
PLL0DV[RFDPHI].
a) With PLL0 disabled, program PLL0 clock source in <CGM_ACn>_SC[SELCTL].
Default source is 16 MHz IRCOSC. Write <CGM_ACn>_SC[SELCTL] = 1 to select XOSC as source.
b) Program PLL0DV[PREDIV], PLL0DV[RFDPHI1], PLL0DV[MFD] and
PLL0DV[RFDPHI].
c) If desired, modify the XOSC_CTL[EOCV] to adjust the external oscillator stabilization count, used when the external oscillator is turned on (by the Mode
Entry module).
d) If necessary, modify the CMU frequency meter values (CMU_MDR and
CMU_FDR) used to monitor the XOSC frequency. XOSC frequency is compared to the IRCOSC source when XOSC is turned on.
2. Turn on XOSC and PLL0.
a) Configure a mode configuration for turning on PLL0 and XOSC. In a mode configuration register (for example, <ME>_DRUN_MC) set
<ME_mode>_MC[XOSCON] = 1 and <ME_mode>_MC[PLL0ON] = 1. If desired, also set <ME_mode>_MC[SYSCLK] = 2 for this new mode configuration to use
PLL0 (PLL0 PHI output) as the sysclk.
b) Enter that mode by two writes to <ME>_CTRL register to enter that mode. This is required even if re-entering the same mode.
3. Wait for the mode transition to complete.
a) Wait for the mode transition to complete by polling <ME>_GS[S_MTRANS] or enabling an interrupt for flag <ME>_IS[I_MTC].
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h. By writing <ME_mode>_MC[PLL1ON] = 0b.
i.
By writing <ME_mode>_MC[PLL1ON] = 1b.
j.
The steps from 1 to 6 describe a recommended way to initialize the PLLs. But the mode_transition from
DRUN to RUNx with the PLLs ON (with PLL1 as sys_clk and PLL0_PHI1 as source of PLL1 and all other clk sources enabled) can be done with a single mode transition. The only software requirement is to ensure that the reference clocks are also configured ON when the derived clock is configured ON in the target mode.
RM0421 Rev 5
RM0421
Note:
Dual PLL digital interface (PLLDIG)
A timer, even if it is the watchdog, should be used to make sure the mode transition completes. Mode transition will NOT complete until:
- XOSC counter expires (if the new mode configuration changes
<ME_mode>_MC[XOSCON] to 1), and
- PLL is locked (if the new mode configuration changes
<ME_mode>_MC[PLL0ON] = 1).
b) Confirm the desired target mode was entered by checking the status of
<ME>_GS[S_CURRENT_MODE].
4. Configure PLL1 and related modules a) With PLL1 disabled, program PLL1 clock source in <CGM_ACn>_SC[SELCTL].
Default is <CGM_ACn>_SC[SELCTL] = which selects XOSC.
b) Program PLL1DV[MFD] and PLL1DV[RFDPHI].
c) If required, program the PLL1FM register with the desired frequency modulation parameters and enable FM modulation, PLL1FM[MODEN] = 1. The PLL1FM register must not be written after PLL1 is enabled and operating in normal mode.
5. Turn on PLL1 a) Configure a mode configuration for turning on PLL1, and keeping XOSC and PLL0 on. In a mode configuration register (for example, <ME>_DRUN_MC), initialize
<ME_mode>_MC[XOSCON] = 1, <ME_mode>_MC[PLL0ON] = 1 and
<ME_mode>_MC[PLL1ON] = 1. If desired, also set <ME_mode>_MC[SYSCLK] =
4 for this new mode configuration to use PLL1 as the sysclk.
b) Enter that mode by two writes to <ME>_CTRL register to enter that mode. This is required even if re-entering the same mode.
6. Wait for the mode transition to complete.
a) Wait for the mode transition to complete by polling <ME>_GS[S_TRANS] or enabling an interrupt for flag <ME>_IS[I_MTC]. A timer, even if it is the watchdog, should be used to make sure the mode transition completes. Mode transition will
NOT complete until:
XOSC counter expires (if the new mode configuration changes
<ME_mode>_MC[XOSCON] = 1), and PLL1 is locked (if the new mode configuration changes <ME_mode>_MC[PLL1ON] = 1).
b) Confirm the desired target mode was entered by checking the status of
<ME>_GS[S_CURRENT_MODE].
Refer to the Mode Entry module chapter for more details.
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