Debug Serial Interprocessor Interface (SIPI). STMicroelectronics SPC58xNx 32-bit Power Architecture microcontroller, SPC58NN84C3, SPC58NN84E7

RM0421

74

Debug Serial Interprocessor Interface (SIPI)

Debug Serial Interprocessor Interface (SIPI)

74.1 Introduction

The Debug Serial Interprocessor Interface (SIPI) is an application layer protocol that runs on top of the LFAST module. It is used by the local device to access the shared memory of a remote device. Debug SIPI defines point-to-point full duplex communication between two nodes, where LFAST works as a physical medium of communication between both the devices.

Debug SIPI implements the Target mode of a communication protocol in hardware. Debug

SIPI can interpret 'read' and 'write' commands received from an LFAST module and convert them into bus accesses to local memory; then send back to the LFAST module either read data or a write acknowledge response. This provides a mechanism for an external device, such as an external tool, to read and write the address map of the local MCU. The bandwidth of these read/write commands is approximately 10 MBytes/second when accessing random addresses using 32-bit transfers.

74.2 Overview

Debug SIPI can access memory mapped resources directly through its AHB master interface. Debug SIPI has four channels, 0, 1, 2, 3. Payload width for all channels is 32 bits.

Figure 2011. SIPI module

SIPI Module

Channel 0*

Channel 1

Channel 2

Channel 3

*

Channel 0 has the highest priority for transmission.

RM0421 Rev 5

3373/4101

3389