RM0421 Mode Entry Module (MC_ME)
65.1.2 Features
The MC_ME includes the following features:
• control of the available modes by the ME_ME register
• definition of various chip mode configurations by the ME_<mode>_MC registers
• control of the actual chip mode by the ME_MCTL register
• capture of the current mode and various resource status within the contents of the
ME_GS register
• optional generation of various mode transition interrupts
• status bits for each cause of invalid mode transitions
• peripheral clock gating control based on the ME_RUN_PC0–7, ME_LP_PC0–7, and
ME_PCTL n registers
• additional core clock gating and boot address control based on the ME_CCTL n and
ME_CADDR n registers
• capture of current peripheral and additional core clock gated/enabled status
• progressive system clock switching when transitioning from a lower power consumption mode to a higher power consumption mode, and vice versa
65.1.3 Modes of operation
Name
The MC_ME is based on several chip modes corresponding to different usage models of the chip. Each mode is configurable and can define a policy for energy and processing power management to fit particular system requirements. An application can easily switch from one mode to another depending on the current needs of the system. The operating modes controlled by the MC_ME are divided into system and user modes. The system modes are modes such as: RESET, DRUN, SAFE, and TEST. These modes aim to ease the configuration and monitoring of the system. The user modes are modes such as: RUN0–3,
HALT0 and STOP0 which can be configured to meet the application requirements in terms of energy management and available processing power. The modes DRUN, SAFE, TEST, and RUN0–3 are the chip software running modes.
Table 1787 describes the MC_ME modes.
Table 1787. MC_ME mode descriptions
Description Entry Exit
RESET
DRUN
This is a chip-wide virtual mode during which the application is not active. The system remains in this mode until all resources are available for the embedded software to take control of the chip. It manages hardware initialization of chip configuration, voltage regulators, clock sources, and flash modules.
system reset assertion from
MC_RGM
This is the entry mode for the embedded software. It provides full accessibility to the system and enables the configuration of the system at startup. It provides the unique gate to enter user modes. BAF, when present, is executed in DRUN mode.
system reset deassertion from
MC_RGM, software request from SAFE, TEST and RUN0 – 3 system reset deassertion from
MC_RGM system reset assertion,
RUN0 – 3, TEST via software, SAFE via software or hardware failure.
RM0421 Rev 5
3053/4101
3113
