RM0421 e200z4256 Core Debug Support
66.9 Basic steps for enabling, using, and exiting External Debug mode
The following steps show one possible scenario for a debugger wishing to use the external debug facilities. This simplified flow is intended to illustrate basic operations, but does not cover all potential methods in depth.
Enabling External Debug mode and initializing debug registers:
• The debugger should ensure that the jd_en_once control signal is asserted in order to enable OnCE operation.
• Select the OCR and write a value to it in which OCR
DR
, OCR
WKUP
, are set to ‘1’. The tap controller must step through the proper states as outlined earlier. This step will place the CPU in a debug state in which it is halted and awaiting single-step commands or a release to normal mode
• Scan out the value of the OSR to determine that the CPU clock is running and the CPU has entered the Debug state. This can be done in conjunction with a Read of the
CPUSCR. The OSR is shifted out during the Shift_IR state. The CPUSCR will be shifted out during the Shift_DR state. The debugger should save the scanned-out value of CPUSCR for later restoration.
• Select the DBCR0 register and update it with the EDBCR0
EDM
bit set.
• Clear the DBSR status bits.
• Write appropriate values to the DBCR0–8, IAC, and DAC registers. Note that the initial write to DBCR0 will only affect the EDM bit, so the remaining portion of the register must now be initialized, keeping the EDM bit set.
At this point the system is ready to commence debug operations. Depending on the desired operation, different steps must occur.
• Optionally, ensure that the values entered into the MSR portion of the CPUSCR during the following steps cause interrupt to be disabled (clearing MSR
EE
and MSR will ensure that external interrupt sources do not cause single-step errors.
CE
). This
To single-step the CPU:
• debugger scans in either a new or a previously saved value of the CPUSCR (with appropriate modification of the PC and IR as described in
Section 66.5.9.2, Control
State Register (CTL)
), with a Go+Noexit OnCE Command value.
• The debugger scans out the OSR with “no-register selected”, Go cleared, and determines that the PCU has reentered the Debug state and that no ERR condition occurred.
To return the CPU to normal operation (without disabling external debug mode)
• The OCR
DR
control bit should be cleared, leaving the OCR
WKUP
bit set.
• The debugger restores the CPUSCR with a previously saved value of the CPUSCR
(with appropriate modification of the PC and IR as described in
Section 66.5.9.2,
Control State Register (CTL) ), with a Go+Exit OnCE Command value.
• The OCR
WKUP
bit may then be cleared.
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e200z4256 Core Debug Support
Note:
RM0421
To exit External Debug mode
• The debugger should place the CPU in the debug state via the OCR
DR asserted, scanning out and saving the CPUSCR.
with OCR
WKUP
• The debugger should write the DBCR0–8 registers as needed, likely clearing every enable except the EDBCR0
EDM
bit.
• The debugger should write the DBSR to a cleared state.
• The debugger should rewrite the DBCR0 with all bits including EDM cleared.
• The debugger should clear the OCR
DR
bit.
• The debugger restores the CPUSCR with the previously saved value of the CPUSCR
(with appropriate modification of the PC and IR as described in
Section 66.5.9.2,
Control State Register (CTL) ), with a Go+Exit OnCE Command value.
• The OCR
WKUP
bit may then be cleared.
These steps are meant by way of examples, and are not meant to be an exact template for debugger operation.
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