LVDS Fast Asynchronous Serial Transmission – High Speed Debug RM0421
75.7.5 Frames supported
Table 1969 provides the frames supported and their permissible payload sizes
Frame type
Table 1969. Frames supported by LFAST interfaces
LCT code
Supported by
1. LFAST Master Tx
2. LFAST Slave Rx
Supported by
1. LFAST Slave Tx
2. LFAST Master Rx
Data frame
Rx – 0100b,1000b – 1011b
Tx – All
Unsolicited frame
ICLC frame
CTS frame
Reserved
0001b
0000b n/a
All others
1. Except the ICLC PING response frame.
YES
YES
YES
NO
—
YES
YES
NO (1)
NO
—
Payload size
(bits)
TX: 96
RX:128
8, 32, 64, 96, 128,
256, 288
8 n/a
—
75.7.6 Frame flow
The following sections describe Data Frame Flow, ICLC Flow and Rx Unsolicited Data Flow.
75.7.6.1 Data flow
LFAST supports the transfer of data between master and slave LFAST devices.
75.7.6.1.1 Data transmit
System Side Module is the initiator of all the Tx data frame to LFAST peer device. Data frame transmit is triggered whenever the Tx Data FIFO has at least one valid frame. The
MCR[DATAEN], MCR[DRFEN] and MCR[TXEN] bits, should be set to enable the transfer of
Tx data.
If MCR[DATAEN] = 0, then the valid frames in the in Tx data FIFO will be ignored for transmission. The Payload Size and channel type of each frame is specified by the System
Side Module interface during transfer of the frame to the LFAST interface. The frame header is stored in the Tx packet FIFO and the payload in the Tx data FIFO.Whenever the Tx FIFO has at least one frame then a data transmit request is made to the Tx arbiter of the LFAST.
Tx block arbitrates the data transmit request and schedules it depending on the priority of all the pending transmit requests. When data request is scheduled by Tx block, the required data is fetched from Tx data FIFO. The number of frames present in the Tx FIFO for transmission is indicated by the bitfield DFSR[TXFCNT].
75.7.6.1.1.1 Programing model for Tx data transmit
1.
Program MCR[DATAEN] = 1, MCR[TXEN] = 1 and MCR[DRFEN] = 1 to enable the Tx path of LFAST device.
2. Select the desired clock rate at which data should be transmitted, using ICLC transfers and appropriate programing of SCR[TDR] bits.
3. Frame present in TX FIFO (Data and Packet FIFO) are sent.
4. TISR[TXDTF] = 1 after each frame transfer.
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75.7.6.1.2 Data receive
LFAST master and slave supports reception of data frame. The received frame is determined to be of data frame type by decoding channel type field of the header present in the received frame. The MCR[DATAEN], MCR[RXEN] and MCR[DRFEN] bits should be set to enable the data frame reception.When MCR[DATAEN] = 0 the received data frames will be ignored and will not be placed in the Rx data FIFO.
The Rx data frames received by Rx block are stored in the Rx FIFO. Whenever the frame is received in the Rx FIFO the System Side Module is indicated by assertion of LFAST Rx
FIFO ready signal. The frame size and the Channel type is passed to the LFAST. The frame boundaries are indicated by start of frame and end of frame signals. The number of unread frames in the Rx Data FIFO are indicated by DFSR[RXFCNT ] . When Rx DATA FIFO is full and cannot accommodate current frame completely, then the remaining data of the Rx frame is discarded.
75.7.6.2 Unsolicited flow
75.7.6.2.1 Unsolicited frame transmit flow
The software is the initiator for unsolicited frames to the LFAST peer device. The unsolicited frame header and payload is programmed into the Unsolicited Data and Control registers.
Once the Payload is programmed UNSTCR[USNDRQ] is set, generating a request for unsolicited frame transfer to the Tx arbiter.
75.7.6.2.1.1 Programing model for unsolicited frame transmit
1.
Program MCR[TXEN] = 1 and MCR[DRFEN] = 1 in the Mode Configuration Register
(MCR) to enable the Tx path.
2. Select the desired clock rate at which data should be transmitted, using ICLC transfers and appropriate programing of SCR[TDR].
3. Read the UNSTCR[USNDRQ].
– If UNSTCR[USNDRQ] = 1 then wait for either of the following:
– UNSTCR[USNDRQ] = 0
– TISR[TXUNSF] = 1.
– If UNSTCR[USNDRQ] = 0 then:
– Program the unsolicited payload in UNSTDR0–UNSTDR8, and can be written up to a payload of frame of a maximum of 288 bits.
– Program the unsolicited frame header in UNSTCR[UNSHDR].
– Program UNSTCR[USNDRQ] = 1.
4. UNSTCR[USNDRQ] is cleared by the Tx Block after the frame transfer.
5. TISR[TXUNSF] = 1 when the frame is transmitted.
75.7.6.2.2 Unsolicited frame receive flow
Whenever an Unsolicited frame is received from the peer device, the following steps are performed:
If UNSRSR[URXDV] = 0 then:
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1.
The payload size field of the header is first saved into the UNSRSR[URPCNT] .
2. The payload is stored in the UNSTDR0–UNSTDR8.
3. UNSRSR[URXDV] = 1 and the RISR[RXUNSF] = 1 indicating the successful reception of the frame.
If UNSRSR[URXDV] = 1 then:
1.
The current unsolicited frame is ignored.
2. RISR[RXUOF] = 1.
Typical steps by the processor after RISR[RXUNSF] = 1 is as follows:
1.
The processor reads UNSRSR to get the payload size of the frame.
2. It then reads the complete frame by reading UNSRDR8–UNSRDR0 for the payload size as received in the frame.
75.7.6.3 ICLC flow
The ICLC (Interface Control Logical Channel) is defined as a separate logical channel type, which is mainly meant for implementing the data rate change in the LFAST interface and initiating the test modes.
75.7.6.3.1
.
ICLC data receive flow
When the bits 4 to 1 of a receive frame are 0000b it indicates that the payload is an ICLC.
ICLC payloads are always 8 bits.
75.7.6.3.1.1 Ping request ICLC
The LFAST slaves ICLC decoder will decode the ping request and set RIISR[ICPRF] = 1.
The software can also write to PICR[PNGREQ] to indicate to the Tx block that a ping response frame needs to be transmitted. The PICR[PNGAUTO] indicates whether Tx block can respond automatically to the request by the LFAST master ICLC Ping Request frame.The Tx block will arbitrate the ping response frame request and send a ping frame with ping data defined by bitfield PICR[PNGPLYD]. Once the ping response frame has been sent the Tx block will set TISR[TXPNGF] and clear PICR[PNGREQ], if set.
75.7.6.3.1.2 LFAST Slaves RxData Interface Slow/Fast ICLC
The LFAST Slaves Rx Interface has two speed modes supported: slow (Low speed) and fast (High speed). The ICLC command will write RIISR[ICRSF] = 1 (Low speed) or
RIISR[ICRFF] = 1 (High speed).
75.7.6.3.1.3 LFAST Slaves TxData Interface Slow/Fast ICLC
The LFAST slaves Tx Interface Controller has two speed modes: slow (Low speed), and fast
(High speed). The ICLC command will write RIISR[ICTSF] = 1 (Low speed) or
RIISR[ICTFF] = 1 (High speed).
75.7.6.3.1.4 Enable/Disable LFAST Slaves TxData Interface ICLC
The ICLC commands, Enable RxData Interface and Disable RxData Interface are decoded and the appropriate enable/disable signal sent to the Tx block Controller. These ICLC command writes RIISR[ICTEF] = 1 and RIISR[ICTDF] = 1. The ICLC Tx enable command will write MCR[TXEN] = 1.
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