Transmit controller. STMicroelectronics SPC58xNx 32-bit Power Architecture microcontroller, SPC58NN84C3, SPC58NN84E7

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RM0421 LVDS Fast Asynchronous Serial Transmission – High Speed Debug

Sleep

Normal mode the receiver current consumption is reduced. Hysteresis in the LR ensures that it continues to present a 1 to the LFAST module.

• Normal

In the Normal state, the LR is primed for reception. Receiver converts differential signals to a single ended logic signal.

LR State

Shutdown

Table 1966. Line Receiver state

LFAST Slave Triggers

(at least one of the following)

– LFAST interface enable assertion/negation

– Programing of LCR[SWOFFLR] or LCR{SWONLR]

– Programing MCR[RXEN] and MCR[TXEN]

– Programing of LCR[SWSLPLR] or LSC[SWWKLR]

Absence of above mentioned conditions

75.7.4 Transmit controller

75.7.4.1 Introduction

The Transmit Controller uses Rx information, status information and error control data and codes them into the appropriate frame structure for transmission to the LD. This includes the synchronization and header, in preparation for the LD, which transmits the frame to peer

LFAST IC at either low or high speed. The Transmit Controller creates a frame structure that is converted to a serial format for the LD.

An arbitration block will determine which message has higher priority data, such as unsolicited, ICLC, ping. The data frames are extracted from the FIFO controller, the unsolicited message from the register block, the CTS messages from the Receive Controller and the ping response from the register block.

The Tx interface has two speed modes:

• Low Speed

• Fast Speed

The Transmit Controller consists of the following blocks as shown in Figure 2061

• Arbitrator

• Framer

• Request Clock Control

The arbitrator will grant access to the framer from the request that has the highest priority.

The framer block will extract the payload data from the granted request source and build the frame (adding synchronization or header if required). The frame is fed into a PISO (Parallel

In Serial Out) and eventually sent to the LD.

RM0421 Rev 5

3427/4101

3448

LVDS Fast Asynchronous Serial Transmission – High Speed Debug

Figure 2061. Transmit controller connections

TRANSMIT CONTROLLER

TXDATA_P

TXDATA_N

PISO

FRAMER

ARBITER

RM0421

REGISTER

(Control and

Status)

TX DATA FIFO TX PACKET FIFO

System Side Interface Module

75.7.4.2 Arbitration

The arbitration block prioritizes between requests from multiple sources like:

• Software programmable registers

• System side interface FIFO

• Rx interface controller

• LFAST Slave: LFAST interface enable (lfast_sysclk_en)

The level of priority for each request is shown in

Table 1967

Request

LFAST interface enable

(lfast_sysclk_en)

Tx Interface disabled

Table 1967. Priority levels for the Transmit controller

LFAST slave priority

Triggering conditions

(at least one of the listed)

– LFAST interface enable (lfast_sysclk_en) is asserted

– LFAST interface enable (lfast_sysclk_en) is negated

– MCR[DRFEN] = 0

– MCR[TXEN] = 0

– MCR[DRFRST] = 1

– MCR[TXARBD] = 1

– LFAST Slave: ICLC frame with payload for “Disable Rx interface” received

3428/4101

RM0421 Rev 5

RM0421 LVDS Fast Asynchronous Serial Transmission – High Speed Debug

Request

Table 1967. Priority levels for the Transmit controller (continued)

LFAST slave priority

Triggering conditions

(at least one of the listed)

Tx Interface speed mode change

Loopback frame in

Loopback mode

Ping response request

Unsolicited frame request

Data frame from Tx

FIFO

Clock mode test

– SCR[TDR] is modified

– LFAST Slave: ICLC frame with payload for changing Rx interface speed received

– TMCR[LPON] = 1

– LFAST Slave: ICLC frame with payload for loopback mode enable received

Note:

Valid only for following TMCR[LPMOD] settings:

LPMOD[2:0] = 011b

LPMOD[2:0] = 100b

– LFAST Slave: ICLC frame with payload for ping request received and

PICR[PNGAUTO] = 1

– LFAST Slave: PICR[PNGREQ] = 1

– Valid only if Last Frame with header b0 = 1 received from the peer

LFAST

– UNSTCR[USNDRQ] = 1

– Tx FIFO contains one or more frames

– Last Frame with header b0 = 1 received from the peer LFAST device

– MCR[DATAEN] = 1

– TMCR[CLKTST] = 0

– LFAST Slave: ICLC frame with payload for clock test mode enable received

Once the arbitrator has granted access to a request, the Framer will commence building the frame. Any new requests for frame or data rate change will not be granted access until the framer has finished transmitting the current frame. If a data rate change request for the Tx interface is received while the Transmit controller is in the middle of sending a frame then the rate change request to the Clocking Module will be delayed. This allows for the frame to be completed before the change in speed mode. This prevents any speed mode change during the transmission of a frame. Once the speed mode request is sent to the Clocking

Module by the Tx Interface Controller, it will then not allow any new requests to be processed for a specific time period defined by the bit field RCDCR[DRCNT].

LD state

Shutdown

Sleep

Normal

Table 1968. Line driver states

LFAST slave triggers

– LFAST interface enable (lfast_sysclk_en) negation/assertion

– Programing LVDS[SWOFFLD] and LVDS[SWONLD]

– ICLC command from LFAST master

– Programing MCR[TXEN] and MCR[DRFEN]

– Programing LVDS[SWSLPLD] and LVDS[SWWKLD]

Absence of above mentioned conditions