Introduction

Chapter 1.

EOS S3 Sensor Processing Platform key features

The EOS S3 is a multi-core, ultra-low power sensor processing system. It is designed for mobile market applications including smartphones, wearables and hearables as well as Internet of Things (IoT) devices. The core of the EOS S3 is QuickLogic's proprietary Flexible Fusion Engine (FFE). To complement the FFE, the EOS

S3 also includes an ARM ® Cortex-M4-F sub-system to enable higher level processing allowing the application processor to offload additional computation requirements to EOS S3. The multi-core approach along with multiple power islands allows the EOS S3 to process sensor data and run algorithms in the most processing and power efficient manner possible.

1.1

Features List

Multi-Core Design

•

Ultra-low power μDSP-like Flexible Fusion Engine (FFE) for always-on, real-time sensor fusion algorithms, an ARM® Cortex® M4-F floating point processor for general purpose processing, and on-chip programmable logic for flexibility and integration of additional logic functions to a single device

•

Multiple, concurrent cores enables algorithm partitioning capability to achieve the most power and computationally efficient sensor processing system-on-a-chip (SoC) in the market

Cortex-M4-F Processor

•

Up to 80 MHz operating speed

•

Up to 512 KB SRAM with multiple power modes, including deep sleep (128 KB of this memory can be used for HiFi sensor batching)

•

Ideal for computationally intensive sensor processing algorithms (continuous heart rate monitor, indoor navigation, always-on voice triggering, etc.)

Third-Generation Flexible Fusion Engine (FFE)

•

Up to 10 MHz operating frequency

•

50 KB control memory

•

16 KB data memory

•

μDSP-like architecture for efficient mathematical computations

•

Ideal for always-on, real-time sensor fusion algorithms (such as pedometer, activity classification, gesture recognition, and others)

Sensor Manager

•

1.5 KB x 18-bit memory

•

Completely autonomous (zero load on the M4-F) initialization and sampling of sensors through hard-wire

I2C or configurable I2C/SPI

Communication Manager

•

Communicates with host applications processor through its SPI Slave interface.

•

Up to 20 MHz

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Dedicated Voice Support

•

Audio support for Pulse Density Modulation (PDM) or I

2

S microphones

•

Optional hardware PDM bypass path to forward microphone data to application processor or Voice

CODEC

•

Dedicated logic for PDM to Pulse Code Modulation (PCM) conversion

•

Dedicated hard logic integration of Sensory Low Power Sound Detect (LPSD) for on-chip voice

Recognition

Programmable Fabric (FPGA)

•

2,400 effective logic cells with 64 Kbit RAM available

•

Eight RAM FIFO controllers

•

Provides capability to add logic functions or augment existing logic functions

Additional Features

•

On-device circuit to support 32.768 kHz clock or crystal oscillator

•

Dual Low-Dropout (LDO) regulators for on-chip regulation

•

Power Management Unit (PMU) for minimizing power in all conditions (idle, deep sleep, and shut down)

•

SPI Master, SPI Slave, I 2 S Master, I 2 S Slave, and I 2 C interfaces

•

Audio support for PDM or I2S microphones

•

Internal codec available for Pulse Density Modulation (PDM) to Pulse Code Modulation (PCM) conversion

•

12-bit ΔΣ Analog-to-Digital Converter (ADC) for battery monitoring

•

2-pin Serial Wire Debug (SWD) port

•

System DMA engine for efficient data movement

• eFuse memory for storing AES Key, voltage trim and other configurable information

Operating System Support

•

Android OS; Contact QuickLogic’s FAE for details

•

Real-Time Operating System (RTOS) compatible

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The following top-level features enable EOS S3 to support Companion and Host use cases.

Table 1-1: EOS S3 Supported features

Feature Details

M4-F Sub-System

Flexible Fusion Engine

Digital Microphone

Support

Packet FIFOs Batching

Memory

Power Management

Unit

Programmable

FPGA Fabric

• Cortex M4-F controller with floating point unit support (M4-F)

• Embedded SRAM (up to 512 KB) for code and data memory

• Vectored interrupt support

• Wakeup interrupt controller

• 2-pin SWD port

• 50 KB control memory

• 16 KB data memory

• Single cycle MAC

• I2S microphone

• PDM microphone

• On-chip PDM-to-PCM conversion

• Hardware bypass path for PDM interface to Host Application Processor

and/or Voice CODEC

• Integrated Low Power Sound Detector from Sensory, Inc.

• 128 KB of M4-F SRAM can be used as HiFi sensor batching memory

• Multiple packet FIFOs to support the FFE to application processor/M4-F

data transfers:

- 8 KB packet FIFO with ring-buffer mode support

- 256 x 32 packet FIFO and two 128 x 32 packet FIFOs

• Low-power mode with fast wake-up

• Programmable power modes (deep sleep, sleep with retention, and active)

• Multiple power domains

• Power sequencing for sleep and wake-up entry and exit

• Software and hardware initiated sleep entry

• Wake-up triggers via internal and external events

• Internal LDO support

• 2,400 effective logic cells with 64 Kbit of RAM, 8 RAM FIFO controllers and

2 GPIO banks

• Supports SPI slave configuration

• Supports reconfiguration from M4-F

• Supports five clocks

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Feature

32 kHz Oscillator with

Real-Time Clock (RTC)

High Frequency

Clock Source

System DMA

SPI Slave

Time Stamping

I2C Master and

Configurable I2C/SPI

Interface

Other Interfaces

UART

Other Peripherals

ADC

LDOs eFuse

Details

• 32 kHz crystal oscillator (external crystal required) with bypass option

• 1 Hz clock generation with compensation register

• RTC function with one alarm register

• Start time of 350μs

• Programmable frequency (2 MHz to 80 MHz) for better frequency resolution

• Calibrated output (using 32 kHz input)

• Startup time of 410μs

• Clock divider can be programmed in 12 bits

• 16 channel DMA allows efficient data movement between processing

elements

• SPI slave application processor communication of up to 20 MHz

• Automatic hardware time stamp on every sensor read in the interrupt mode

• Up to eight sensor interrupt captured time-stamps (8-bit)

• Main time stamp of 30 bits for M4-F processor and 24 bits for FFE

• Resolution of 1ms

• I2C master and SPI master with programmable clock pre-scalar

• Option to disable multi-master support and slave-inserted wait for shorter

SCL cycles

• Configurable for two I2C Masters or one I2C Master and one SPI Master

• SPI master for interfacing with serial flash memories and other external

SPI-based peripherals of up to 20 MHz

• I2S Slave Transmitter for downloading audio samples to Host Application

Processor

• Serial support for M4-F debug and code development

• Communication with UART-based external peripherals

• Timers

• Watchdogs

• GPIO controllers

• Low sampling rate

∆Σ

12-bit

• On-chip LDO for system logic

• Separate on-board LDO for memory

• On-chip eFuse for storing fuse data for in-chip performance tuning and

security key bits

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Feature

Integrated Software

Debug Interface

Packaging Options

Details

• 2-pin SWD port for access to the following memory mapped resources:

- M4-F internal registers and memories

- FFE and Sensor Manager memories

- FFE control registers

- On-chip programmable logic memories

- On-chip programmable logic designs through generic AHB bus

- All memory map peripherals such as timers, WDT, SPI master, etc.

- I2C master used for I2C sensor debug

- Multiplexed dedicated parallel debug interface

• 42-ball WLCSP (2.66 mm x 2.42 mm x 0.51 mm) (27 user I/O, 2 VCCIO

banks)

• 64-ball BGA (3.5 mm x 3.5 mm x 0.71mm) (46 user I/O, 2 VCCIO banks)

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