Memory Protection Unit (MPU). Qwiic QuickLogic Thing Plus - EOS S3

3.7

Memory Protection Unit (MPU)

In power domain: M4

The Memory Protection Unit has:

•

Eight memory regions.

•

Sub Region Disable (SRD), enabling efficient use of memory regions.

•

The ability to enable a background region that implements the default memory map attributes.

The MPU is part of the ARM core.

Use of the MPU is controlled by the MPU Config register:

Base address = see section 3.6.2

Table 3-22: MPU Config Register in ExtM4Reg space

0x014 CONFIG2

MPU_DISABLE

31:0

1

R/W/C

RW

Default

0x0

Description

If asserted the MPU is invisible and unusable. Set HIGH to disable the

MPU. Set LOW to enable the MPU.

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