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Chapter 26.
Sensor sub-system registers
The Sensor Manager is programmed using the QuickLogic compiler for the Sensor Manager instruction set.
Control for the Sensor Hub is also performed through direct operations with FFE registers. The I
2
C and SPI interfaces are accessed by indexed write and read operations performed through FFE registers. For example, addressing interfaces on the Wishbone buses is performed by write to the FFE WB_ADDR register.
The following describes the FFE register set.
26.1
FFE registers
Offset Name/Field
0x000 WB_ADDR
Addr
RESERVED slave_sel
0x004 WDATA
0x008 CSR spi0_mux_sel i2c1_mux_sel i2c0_mux_sel
OVFL
BUSY mux_wb_sm wb_ms_wen wb_ms_start
Bits
7:0
2:0
5:3
7:6
7:0
7:0
7
6
5
4
3
2
1
0
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
WO
RW
RW
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
Wishbone Bus Master address selection
Slave address register via Wishbone Bus master
Reserved
The two MSBs select which slave is accessed by Wishbone Bus master
0x0 = I2C_0
0x1 = I2C_1
0x2 = SPI_0
This register is for writes to an I2C slave. It is the I2C slave data register selected via the
Wishbone Bus master
Control and Status register
SPI_0_Master wishbone control mux select
1 = Control from Wishbone Bus Master
0 = Control from SM1
I2C_1 wishbone control mux select
1 = Control from Wishbone Bus Master
0 = Control from SM1
I2C_0 wishbone control mux select
1 = Control from WB Master
0 = Control from SM0 ffe_push_overflow
WB busy
Mux select choosing between SM and WB masters
1 = WB master
0 = SM WB master)
WB master write enable
1 = Write
0 = Read
WB master start transactions. This bit is self clear
Retent ion?
No
No
No
EOS S3 TRM (r1.01a) Confidential Page 253
Offset Name/Field
0x00C RDATA
0x014 SRAM_test_reg1
DM1_RME
DM1_TEST1
DM0_RM
DM0_RME
DM0_TEST1
CM2k_RM
CM2k_RME
CM2k_TEST1
CM8k_RM
CM8k_RME
CM8k_TEST1
SM0_RM
SM0_RME
SM0_TEST1
SM1_RM
SM1_RME
SM1_TEST1
0x018 SRAM_test_reg2
DM3_RM
DM3_RME
DM3_TEST1
DM2_RM
DM2_RME
DM2_TEST1
DM1_RM
0x020 FFE_CSR i2c2_sel
EOS S3 TRM (r1.01a)
31:0
31
30
29:26 RW
25 RW
24 RW
23:20 RW
RW
RW
RW
19
18
RW
RW
17:14 RW
13 RW
12
11:8
7
RW
RW
RW
11
10
9:6
5
6
5:2
1
0
RW
RW
RW
RW
31:0 RW
15:12 RW
4
3:0
31:0
RW
RW
RW
RW
RW
RW
RW
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Bits Type Default Description
7:0
0
RO
RW
0x0
0x0
This register is for reads from an I2C slave.
Read data from I2C to WB master is registered
SRAM test control register 1
DM1_RME control to FFE SRAM module
DM1_TEST1 control to FFE SRAM module
DM0 RM [3:0] control to FFE SRAM module
DM0_RME control to FFE SRAM module
DM0_TEST1 control to FFE SRAM module
CM2k_RM [3:0] control for FFE SRAM
CM2k_RME control for FFE SRAM
CM2k_TEST1 control for FFE SRAM
CM8k_RM [3:0] control for FFE SRAM
CM8k_RME control for FFE SRAM
CM8k_TEST1 control for FFE SRAM
SM0_RM[3:0] control for FFE SRAM
SM0_RME control for FFE SRAM
SM0_TEST1 control for FFE SRAM
SM1_RM[3:0 control for FFE SRAM
SM1_RME control for FFE SRAM
SM1_TEST1 control for FFE SRAM
SRAM test control register 2
DM3 RM [3:0] control to FFE SRAM module
DM3_RME control to FFE SRAM module
DM3_TEST1 control to FFE SRAM module
DM2 RM [3:0] control to FFE SRAM module
DM2_RME control to FFE SRAM module
DM2_TEST1 control to FFE SRAM module
DM1 RM [3:0] control to FFE SRAM module
FFE Control and Status Register
1: selects i2c 2
0: selects i2c 1
Retent ion?
No
No
Yes
No
Confidential Page 254
Offset Name/Field
I2c0_dyn_pullup_en
I2c1_dyn_pullup_en
I2c2_dyn_pullup_en
RESERVED
0x038 FFE_DEBUG_COMBINED
SM0_SM_debug
SM1_SM_debug
FFE_debug
0x100 COMMAND
RUN_FFE_ONCE
RESERVED
RUN_SM0_ONCE
RUN_SM1_ONCE
0x108 INTERRUPT
SM_MULT_WR_INTR
FFE_OVERRUN
RESERVED
RESERVED
FFE_SM1_OVERRUN
FFE_SM0_OVERRUN
Bits Type
31:4
31:0
7:0
1
2
3
RW
RW
RW
15:8 RO
23:16 RO
31:0
RO
RO
RO
0
1
2
3
31:0
0
1
2
3
4
5
WO
WO
WO
WO
RW1
C
RW1
C
RO
RO
RW1
C
RW1
C
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
I2c0 dynamic pull-up enable
I2c1 dynamic pull-up enable
I2c2 dynamic pull-up enable
Reserved
Combined FFE debug signals
Sensor memory 0 debug signals
Sensor memory 1 debug signals
FFE debug signals
When a ‘1’ is written to this location, causes the FFE to execute one complete run of its algorithm; reads as 0
Reserved
When a ‘1’ is written to this location, causes
SM0 to run once; reads as 0
When a ‘1’ is written to this location, causes
SM1 to run once; reads as 0
This bit is set when an FFE tries to write to more than one FIFO simultaneously. The
FIFO PUSH value must be one hot, with only one pushd asserted.
This bit is set when the FFE does not complete running its code (the algorithm) by the time the next sample period begins. This bit can only be cleared by issuing a device reset (software reset, or global reset via the
Reset pin).
Reserved
Reserved
This bit is set when SM1 does not complete the algorithm by the time the next sample period begins. This bit can only be cleared by issuing a device reset (software reset, or global reset via the Reset pin).
This bit is set when SM0 does not complete the algorithm by the time the next sample period begins. This bit can only be cleared by issuing a device reset (software reset, or global reset via the Reset pin).
Retent ion?
No
No
Yes
EOS S3 TRM (r1.01a) Confidential Page 255
Offset Name/Field
I2C_MS_1_ERROR
I2C_MS_0_ERROR
CM_8k_LP_INTR
DM0_LP_INTR
DM1_LP_INTR
SM0_LP_INTR
SM1_LP_INTR
FFE_BP_MATCH_INTR
Reserved
PKFB_OVF_INTR
SM0_BP_MATCH_INTR
SM1_BP_MATCH_INTR
SPI_0_MS_INTR
CM_2k_LP_INTR
DM2_LP_INTR
DM3_LP_INTR ahbm_bus_error_intr
0x10c INTERRUPT_ENABLE
SM_MULT_WR_INTR_EN
EOS S3 TRM (r1.01a)
15
16
17
18
19
20
21
22
31:0
0
RW1
C
RW1
C
RW1
C
RW1
C
RW1
C
RW1
C
RW1
C
RW1
C
Bits Type Default Description
6
7
8
9
10
11
12
13
14
RW1
C
RW1
C
RW1
C
RW1
C
RW1
C
RW1
C
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
This bit is set when the I2C Master receives a NACK when transmitting a device address.
The I2C Master is used by the Sensor
Manager to retrieve sensor data.
This bit is set when the I2C Master receives a NACK when transmitting a device address.
The I2C Master is used by the Sensor
Manager to retrieve sensor data.
This bit is set when there is an access to the memory while it is in low power (deep sleep or shut down)
This bit is set when there is an access to the memory while it is in low power (deep sleep or shut down)
This bit is set when there is an access to the memory while it is in low power (deep sleep or shut down)
This bit is set when there is an access to the memory while it is in low power (deep sleep or shut down)
This bit is set when there is an access to the memory while it is in low power (deep sleep or shut down)
This bit is set when there is a break point match in FFE
Reserved
RW1
C
RW1
C
RW1
C
RW
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
This bit is set when the FFE pushes to the
PKFB causing an overflow
This bit is set when there is a break point match in SM0
This bit is set when there is a break point match in SM1
This bit is set when there is an interrupt request from SPI_0_Master for sensor
This bit is set when there is an access to the memory while it is in low power (deep sleep or shut down)
This bit is set when there is an access to the memory while it is in low power (deep sleep or shut down)
This bit is set when there is an access to the memory while it is in low power (deep sleep or shut down)
This bit is set when there is a bus error on the AHB bus (HRESP=1).
Interrupt enabled
0: mask interrupt
1: enable interrupt
Retent ion?
Yes
Confidential Page 256
Offset Name/Field
FFE_OVERRUN_EN
RESERVED
RESERVED
FFE_SM1_OVERRUN_EN
FFE_SM0_OVERRUN_EN
I2C_MS_1_ERROR_EN
I2C_MS_0_ERROR_EN
CM_8k_LP_INTR_EN
DM0_LP_INTR_EN
DM1_LP_INTR_EN
SM0_LP_INTR_EN
SM1_LP_INTR_EN
FFE_BP_MATCH_INTR_EN
Reserved
PKFB_OVF_INTR_EN
SM0_BP_MATCH_INTR_EN
SM1_BP_MATCH_INTR_EN
SPI_MS_INTR_EN
Bits Type Default Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Interrupt enabled
0: mask interrupt
1: enable interrupt
Reserved
Reserved
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled for I2C_1_Master
0: mask interrupt
1: enable interrupt
Interrupt enabled for I2C_0_Master
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Reserved
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Retent ion?
EOS S3 TRM (r1.01a) Confidential Page 257
Offset Name/Field
CM_2k_LP_INTR_EN
DM2_LP_INTR_EN
DM3_LP_INTR_EN ahbm_bus_error_intr_en
0x110 STATUS
SM0_BUSY
SM1_BUSY
FFE_BUSY
Reserved
FFE_BG_FLAG
FFE_FG_FLAG
0x114 MAILBOX_TO_FFE
MAILBOX_TO_FFE
0x120 SM_RUNTIME_ADDR
SM_RUNTIME_ADDR
0x124 SM0_RUNTIME_ADDR_CTRL
SM0_RUNTIME_ADDR_NEW
0x128 SM1_RUNTIME_ADDR_CTRL
SM1_RUNTIME_ADDR_NEW
EOS S3 TRM (r1.01a)
Bits Type Default Description
19
20
21
22
31:0
0
1
5
31:0
2
3
4
31:0
31:0
9:0
31:0
0
31:0
0
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
Interrupt enabled
0: mask interrupt
1: enable interrupt
This bit is set whenever the Sensor Manager
0 is busy.
This bit is set whenever the Sensor Manager
1 is busy.
This bit is set whenever the FFE is busy.
Reserved.
This is the FFE background thread status
This is the FFE foreground thread status
This is the M4 Mailbox register to the FFE.
This register can be set by system software to send a message or configuration information to the FFE as it runs its algorithm, thus affecting the algorithm while it is running. A special instruction may be used in the algorithm to read this mailbox register.
SM0/SM1 run time address
Write a '1' to Toggle signal used to signal when a new value has been written
Write a '1' to Toggle signal used to signal when a new value has been written
Retent ion?
No yes
No
No yes
Confidential Page 258
Offset Name/Field
0x12c SM0_RUNTIME_ADDR_CUR
SM0_RUNTIME_ADDR_CUR
0x130 SM1_RUNTIME_ADDR_CUR
SM1_RUNTIME_ADDR_CUR
0x140 SM0_DEBUG_SEL
SM0_DEBUG_SEL
0x144 SM1_DEBUG_SEL
SM1_DEBUG_SEL
0x148 FFE_DEBUG_SEL
FFE_DEBUG_SEL_SM0
FFE_DEBUG_SEL_SM1
FFE_DEBUG_SEL_FFE0
FFE_TOP_DEBUG_SEL
0x150 FFE_BREAK_POINT_CFG
FFE_BP_EN
FFE_FORCE_STOP
FFE_BreakPt_Sw_Brk
0x154 FFE_BREAK_POINT_CONT
SM1_BP_CONT
SM0_BP_CONT
Bits Type Default Description
31:0
9:0
31:0
9:0
31:0
7:0
31:0
7:0
31:0
7:0
15:8 RW
23:16 RW
RW
RW
RO
RO
RW
25:24
31:0
0
1
2
31:0
2
1
RW
RW
RW
RW1
T
RW
RW
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
SM0 current program counter
SM1 current program counter
SM0 Debug selection
SM1 Debug selection
SM0 LS debug selection
SM1 LS debug selection
FFE LS debug selection
FFE_TOP MS debug selection
0: SM0
1: SM1
2: FFE
"break point" execution
0 : Disabled
1 : Enabled
This causes the FFE to immediately halt execution.
Causes the signal to toggle when written with a '1' in this bit position.
This is a single, host controlled input toggle signal, Break Point Match Continue.
Software uses this toggle signal to resume code execution from the Break Point condition.
This is a single, host controlled input toggle signal, Break Point Match Continue.
Software uses this toggle signal to resume code execution from the Break Point condition.
Yes
Retent ion?
No
No
No
No yes
No
EOS S3 TRM (r1.01a) Confidential Page 259
Offset Name/Field
FFE_BP_CONT
0x158 FFE_BREAK_POINT_STAT
SM1_BP_MATCH
SM0_BP_MATCH
FFE_BP_MATCH
0x160 FFE_BP_XPC_0
FFE_BP_XPC_0
0x164 FFE_BP_XPC_1
FFE_BP_XPC_1
0x168 FFE_BP_XPC_2
FFE_BP_XPC_2
0x16C FFE_BP_XPC_3
FFE_BP_XPC_3
Bits Type Default Description
0
31:0
2
1
31:0
13:0
31:0
13:0
0
31:0
13:0
31:0
13:0
RW
RO
RO
RW
RW
RW
RW
RO
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
This restarts FFE code execution following a pause due to reaching a "break point".
SM Break Point Match signal output to the host that notifies the host that the break point condition has been detected.
SM Break Point Match signal output to the host that notifies the host that the break point condition has been detected.
This signals that a "break point" has been reached and FFE execution is paused.
These registers hold the xPC (program counter) address "break points".
These registers hold the xPC (program counter) address "break points".
These registers hold the xPC (program counter) address "break points".
These registers hold the xPC (program counter) address "break points".
Retent ion?
No
Yes
Yes yes
Yes
EOS S3 TRM (r1.01a) Confidential Page 260
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