Memory concepts in the S3 architecture. Qwiic QuickLogic Thing Plus - EOS S3

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2.5

Memory concepts in the S3 architecture

The S3 gives designers several ways to store data:

SRAM banks

Packet FIFOs (PKFB SRAM)

SRAM within the FPGA fabric

2.5.1

SRAM banks and their usage scenarios

There are four SRAM banks for the M4. Initial program load from external flash will go into the RAM banks.

The first three of the banks are in the M4 power domain and the fourth one is in its own power domain.

Special system design aspects of the fourth SRAM bank

Because the fourth bank is in its own power domain, this allows storing data even when the M4 is asleep.

Also, the fourth bank is accessed from a bus arbiter spanning both the M4 AHB bus and the AON AHB bus.

This allows other system elements to access this RAM at any time by means of the AON AHB bus. For example, HiFi sensor data batching can be done to this always-on 128 KB RAM (as well as to other storage such as the Packet FIFO or RAM in FPGA.

2.5.2

Packet FIFOs

There are four packet FIFOs of varying sizes of SRAM. These can be used to handle I/O streams from eternal sensors or to or from an AP.

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8 KB packet FIFO with ring-buffer mode support

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256 x 32 packet FIFO

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Two 128 x 32 packet FIFOs

This RAM is in the SRAM PF power domain.

2.5.3

SRAM in the FPGA

The FPGA area contains some dedicated SRAM, which is in the FB power domain. Users may apply it in designs as needed.

2.5.4

Memory power domains and sleep modes

In the S3 there are 31 major power domains (which include the M4 SRAMs) and 19 other, separate, SRAM power domains.

Each of the memory types (M4 SRAM, FIFO SRAM, and FPGA SRAM) has its own available types of power modes. This gives designers flexibility in creating application functions.

These characteristics are discussed in various chapters that related to device Power modes, controls as well as the chapters for the topics of SRAM, Packet FIFO, and FPGA.

2.6

Support for designs with an Applications Processor

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The S3 design features a low-power Communication Manager sub-system for efficient communication with an AP

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The CM's TLC can talk to an AP through a SPI slave interface that can operate at up to 20 MHz

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The TLC can use the Packet FIFO buffer

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S3 interrupts can be routed to the AP

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The AP reboot interrupt input, can inform the S3 of host status