SPI Configuration Register (SPICR) (Offset 0x02). Qwiic QuickLogic Thing Plus - EOS S3

25.5.2.4

SPI Configuration Register (SPICR) (Offset 0x02)

The SPI control register (SPICR) should be written to only when a transaction is not in progress. This register configures the SPI Host Controller. It controls the mode of operation (Master/Slave), the phase and polarity of the clock, and the transfer type (LSB or MSB first).

Bit[7]

Bits

0

1

2

3

4

5

6

7

Bit[6]

Type

R/W

-

R/W

R/W

R/W

R/W

R/W

R/W

Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]

SPE SPIE BIDIROEn SPC0 CPOL CPHA Reserved LSBFE

Bit 1 is not implemented (reads or writes to these bits are not implemented). After system reset the following register bits are set to the default values.

Default Description

0

LSBFE:

1 = LSB is transferred first

0 = MSB is transferred first

Reserved

0

0

0

0

0

0

0

CPHA: SPI Clock Phase Bit.

When CPOL = 0:

0 = data are captured on the clock's rising edge and

data is propagated on a falling edge

1 = data are captured on the clock's falling edge and

data is propagated on a rising edge

When CPOL = 1:

0 = data are captured on the clock's falling edge and

data is propagated on a rising edge

1 = data are captured on the clock's rising edge and

data is propagated on a falling edge

CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle

CPOL: SPI clock polarity bit. This bit selects an inverted or non-inverted

SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values.

1 = Active-low clocks selected; SCK idles high.

0 = Active-high clocks selected; SCK idles low.

SPC0: Serial pin control bit 0. This bit enables bidirectional pin configuration.

BIDIROEn: Output enable in the bidirectional mode.

0 = Output buffer enabled.

1 = Output buffer disabled.

SPIE: SPI interrupt enable bit. This bit enables SPI

Interrupts each time the IR or IW status flag is set.

1 = SPI interrupts enabled.

0 = SPI interrupts disabled

SPE: SPI system enable bit. This bit enables the SPI system and dedicates the SPI port pins to SPI system

Functions.

1 = SPI port pins are dedicated to SPI functions.

0 = SPI disabled

EOS S3 TRM (r1.01a) Confidential Page 247