Sensor Processing (FFE) Sub-System Low Power Modes. Qwiic QuickLogic Thing Plus - EOS S3
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32.8
Sensor Processing (FFE) Sub-System Low Power Modes
The sensor processing (FFE) sub-system is typically turned off until sensor reading is needed. The sub-system may be woken up by an interrupt or periodically to poll the sensors. The following diagram illustrates the sequence for periodically turning on the FFE power domain.
1.
The SPT generates the FFE kick off (wake up) signal with the period FFE_TO_PERIOD.
2.
Prior to FFE kick off, PMU turns on the FFE power domain. This is the PMU kick off pulse.
3.
FFE will start processing after PMU_TO_PERIOD to wait for the FFE power domain to stabilize.
PMU will turn off FFE power domain once the FFE busy signal is de-asserted.
FFE_TO_PERIOD
FFE Kick Off
PMU_TO_PERIOD
PMU Kick Off
FFE Power Domain
FFE BUSY
Figure 32-4: FFE Wake up/Shutdown Sequence
32.9
SDMA Low Power Mode
The SDMA_BRIDGE monitors how many cycles SDMA stays in IDLE state. If SDMA stays in IDLE state longer than the SDMA_BRIDGE.SDMA_PWRDN_CNT threshold, SDMA_BRIDGE will send a power down request to
PMU to shut down the SDMA power domain.
EOS S3 TRM (r1.01a) Confidential Page 307
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Table of contents
- 17 Introduction
- 17 EOS S3 SENSOR PROCESSING PLATFORM KEY FEATURES
- 17 Features List
- 22 THE S3 HIGH-LEVEL ARCHITECTURE
- 23 S3 block diagram with main sub-systems
- 24 The top-level internal system elements and peripherals in the S
- 24 List in alphabetical order
- 25 List by functional groups
- 27 Accessing elements and peripherals
- 27 Key blocks in the main sub-systems
- 27 Cortex-M4-F main modules
- 27 Voice / audio processor main modules
- 27 Sensor processor main modules
- 28 FPGA main modules
- 28 Communication Manager Modules
- 28 Buses in the S3: AHB, secondary buses, and bridges
- 29 Memory concepts in the S3 architecture
- 29 SRAM banks and their usage scenarios
- 29 Packet FIFOs
- 29 SRAM in the FPGA
- 29 Memory power domains and sleep modes
- 29 Support for designs with an Applications Processor
- 30 Support for standalone designs (Host Mode operation)
- 31 ARM Cortex-M4F Sub-System & Core IO
- 31 ARM CORTEX-M4F SUB-SYSTEM
- 31 Description
- 32 ARM Cortex-M4-F IP Configuration
- 33 ARM Cortex-M4-F Processor
- 33 Cortex-M4-F Processor Block Diagram
- 34 Cortex-M4-F Core Peripherals
- 34 Peripheral ID, Component ID, Designer ID, and Part and Revision Number
- 36 CPUID register
- 37 Buses
- 37 M4 AHB
- 37 AHB2APB bus bridges
- 38 Memory
- 38 Memory Map
- 41 Memory Address Decoding
- 44 M4 SRAM
- 45 SRAM Configuration
- 46 Registers
- 50 Memory Protection Unit (MPU)
- 51 MPU Registers
- 52 Nested Vectored Interrupt Controller (NVIC)
- 53 List of interrupts
- 53 NVIC Registers
- 54 Timers
- 54 M4 Timer
- 55 M4 Timer Registers
- 55 SysTick Timer
- 55 SysTick Register
- 56 Watchdog Timer (WDT)
- 56 WDT Registers
- 58 SYSTEM BUSES
- 58 M4 AHB bus
- 58 AON AHB bus
- 58 AHB2APB bus bridges
- 59 MEMORY
- 59 FIFOs
- 59 Packet FIFO
- 60 Registers
- 68 System DMA Controller (SDMA)
- 68 SDMA Registers
- 74 SDMA_BRIDGE Registers
- 76 VP DMAC
- 77 VP DMAC registers
- 79 INTERRUPT HARDWARE
- 79 Wake-up Interrupt Controller (WIC)
- 79 Registers
- 80 ON-CHIP LDO POWER REGULATION
- 80 Design case: Internal Voltages Supplied by Two LDOs
- 81 Design case: Internal Voltages Supplied by Single LDO
- 82 Design case: Internal Voltages Supplied by External Source
- 83 POWER DOMAINS IN THE S
- 83 Main power domains in the S
- 84 AON A0 Always ON power domain
- 84 A1 domain
- 84 M4 power domain
- 84 M4 SRAMs power domain
- 85 SRAM Power Domains
- 86 CLOCK OSCILLATORS, SYSTEM CLOCKS, AND TIMERS
- 86 Introduction
- 86 Oscillators
- 86 The Slow Oscillator
- 86 Design using crystal
- 86 Design using external clock instead of crystal
- 87 The Fast Oscillator
- 87 Frequency selection
- 87 Selection of source for internal HSO_Clock
- 88 CLOCK DOMAINS, CLOCK CHAINS, AND THE CRU
- 88 Clock sources
- 88 Clock divider chains and the CRU
- 93 Clock Gating
- 93 Clock Reset Unit
- 93 CRU Control Register Background Information
- 96 CRU Registers
- 112 Core Special IO Functions & GPIO
- 112 CORE SPECIAL IO FUNCTIONS & GPIO OVERVIEW
- 113 COMMUNICATION MANAGER (CM) SUB-SYSTEM
- 113 CM Architecture
- 113 Top Level Controller in the CM
- 114 Communication Manager DMA controller
- 114 Communication Manager Theory of Operation
- 115 SPI_SLAVE INTERFACE IN THE CM
- 115 Introduction
- 115 Architecture
- 115 Usage Roles
- 116 SPI Interface Protocol for the SPI_Slave block
- 116 Basic Read/Write Transfers
- 117 Device ID Read
- 118 Transfer Types
- 118 Transfers to TLC Local Registers
- 118 Transfers from Packet FIFOs
- 118 Transfers to M4 Memory Address Space
- 118 Basic AHB Transfer Restrictions
- 119 AHB Memory Read
- 119 AHB Memory Burst Write
- 120 AHB Memory Burst Read
- 121 Communication Manager Components Registers
- 124 UART registers
- 133 CLOCKING AND TIMING ELEMENTS
- 133 RTC (Real Time Clock)
- 133 RTC Registers
- 133 SPT (Simple Periodic Timer)
- 134 Error Correction for 1mS Timer
- 135 Timeout Event Counter
- 135 Time Stamp Counters
- 135 PMU and FFE Wakeup
- 136 Registers for SPT and RTC
- 144 ANALOG IP (AIP) BLOCK
- 144 Real time clock
- 144 HS_OSC
- 144 AIP group registers
- 151 ANALOG-TO-DIGITAL CONVERTER (ADC)
- 151 Overview
- 151 Functional Description
- 151 PCB Layout Recommendations
- 152 Example Application
- 152 ADC Registers
- 153 S3 GPIO
- 153 IO Mux and GPIO Introduction
- 153 IO Mux Overview
- 154 How to Select Output Function
- 158 Selecting an Input Function
- 161 IOMux Assignments
- 170 GPIO Registers
- 211 PAD_x CTRL register Description
- 212 Voice / Audio Processing subsystem
- 212 VOICE / AUDIO PROCESSING SUB-SYSTEM
- 212 Introduction
- 212 General characteristics
- 213 Power
- 213 List of operating modes
- 213 Application example in system with Application Processor
- 214 Sub-system Architecture
- 214 Voice / Audio Processing sub-system internal block diagram
- 215 Pulse Density Modulation (PDM) Interface
- 215 S) Interface
- 215 Low-Power Sound Detect (LPSD)
- 216 PDM Internal CODEC Mode
- 217 PDM External CODEC Mode
- 218 PDM VoiceQ Mode
- 219 S Direct Mode
- 219 S Sub-Sample Mode
- 220 Voice / audio processing sub-system registers
- 225 Sensor Processing Hub Sub-system
- 225 SENSOR PROCESSING HUB SUB-SYSTEM
- 225 Introduction
- 225 Sensor Processing Hub Sub-System Architecture
- 225 Block diagram
- 226 Key elements in the Sensor Processing Hub sub-system
- 226 AHB master bridge for the Sensor Processing Hub
- 226 Related system components: Packet FIFO
- 227 General characteristics
- 227 Key functional characteristics
- 228 Power
- 229 SENSOR PROCESSING HUB THEORY OF OPERATION
- 229 Control and Flow
- 229 Operating flow
- 231 SM Mailboxes
- 231 Sampling and Timing
- 231 Time Stamping
- 232 FLEXIBLE FUSION ENGINE (FFE)
- 232 Architecture of the FFE
- 233 µDSP general functions
- 233 Instruction Memory
- 233 Data Memory
- 233 Theory of operation for the FFE
- 233 Power control
- 234 Mailboxes
- 234 Data handling
- 235 SENSOR MANAGERS
- 235 Sensor Manager Internal Architecture
- 235 Sensor Manager Memory
- 235 Structure of Sensor Manager memory
- 236 Related system elements
- 236 Wishbone Bus
- 236 C interfaces
- 237 C Master
- 237 SPI_0_Master
- 238 SPI_0_MASTER
- 238 Architecture and Operation
- 239 I/O signals for the SPI_0_Master block
- 240 Master / slave clocking
- 240 SPI Transactions
- 240 SPI Write Cycle
- 241 SPI Read Cycle
- 241 SPI Multiple Read Cycle
- 242 SPI 3 wire configuration
- 242 SPI corner cases
- 242 Clock Phase and Polarity Controls
- 242 Transfer Format for CPHA
- 245 SPI_0_Master Registers
- 245 Address Map
- 245 Register Descriptions
- 245 Register: SPI Baud Register LSB (SPIBR LSB) (Offset 0x00)
- 245 Register: SPI Baud Register MSB (SPIBR MSB) (Offset 0x01)
- 246 SPI Configuration Register (offset 0x02)
- 247 SPI Configuration Register (SPICR) (Offset 0x02)
- 248 Transmit Register (Offset 0x03) - Write only
- 248 Receive Register (Offset 0x03) -Read Only
- 248 SPI Command (Transfer) Register (Offset 0x04) -Write Only
- 249 SPI Interrupt / Status Register (Offset 0x04) -Read Only
- 249 Slave Select Register (Offset 0x05)
- 250 SPI bit / clock control register (Offset 0x06)
- 250 Number of SPI clocks required after CSn is de-activated (Offset 0x07)
- 251 Programming
- 251 SPI Host Operation
- 251 Read Operation
- 252 Write Operation
- 253 SENSOR SUB-SYSTEM REGISTERS
- 253 FFE registers
- 261 FPGA Sub-system
- 261 FPGA SUB-SYSTEM
- 261 Introduction
- 261 Power
- 261 Sub-system Architecture
- 261 FPGA sub-system components
- 262 Functional Description
- 262 Logic Cell
- 263 RAM/FIFO
- 266 FIFO Controller
- 270 Distributed Clock Networks
- 270 Global Clocks
- 273 Configurable Input/Output Signals
- 274 Multipliers
- 275 Interface to the On-Chip Programmable Logic
- 275 S3 Platform Interface
- 276 FPGA Use
- 276 FPGA Configuration Control
- 276 FPGA sub-system registers
- 277 Debug
- 277 M4-F DEVELOPMENT AND DEBUG SUPPORT ELEMENTS
- 277 Integrated Configurable Debug
- 277 Serial Wire Debug port (SWD)
- 277 Debug Configuration
- 278 Debug Bootstrap Configuration
- 278 Companion/High-Level O/S Host Configuration (Application Processor in System)
- 278 Host Configuration (the EOS S3 system operating as Host)
- 279 DAP accessible ROM table
- 279 AHB-AP
- 279 Instrumentation Trace Macrocell (ITM)
- 279 ITM Registers
- 281 Data Watchpoint and Trace (DWT)
- 281 Registers
- 283 Flash Patch and Breakpoint Unit (FPB)
- 283 FPB Registers
- 284 Trace Port Interface Unit (TPIU)
- 284 TPIU Registers
- 285 Misc. Resources
- 285 EFUSE
- 285 eFuse Registers
- 287 System Considerations
- 287 SYSTEM CONFIGURATION FOR START-UP
- 287 System design modes
- 287 Selecting system design mode on boot
- 287 Configuration for debugging
- 288 Configuring to identify that M4 Serial Wire Debugger is present
- 288 Configuring M4 Serial Wire Debug Port pin assignment
- 288 Configuring clock oscillators
- 288 Boot-time configuration for use of internal HS_Osc or external driver for HS_Osc
- 289 I/O configuration
- 289 LDO configuration
- 289 FPGA configuration
- 290 RESET, START-UP, AND INTERRUPTS
- 290 Reset
- 291 Startup flow for Companion Mode
- 291 Startup flow for Host Mode
- 291 Host mode boot load from external flash
- 292 Interrupts
- 293 Functions of the NVIC and WIC interrupt controllers
- 293 Interrupt Sources
- 294 POWER MODES
- 294 Introduction
- 295 Power Modes in the S
- 295 Comparison of Power Modes
- 297 Methods for entering Low Power Modes
- 297 Software sources for initiating low-power modes
- 299 Hardware sources for initiating low-power modes
- 299 Methods for exiting Low Power Modes
- 300 Software sources for exiting low power mode
- 301 Hardware sources for exiting low power mode
- 302 M4 Sub-System Low Power Modes
- 302 M4-F Sleep Modes
- 303 M4 SRAM power domains and sleep Modes
- 303 M4 SRAM Sleep Modes: LPMF and LPMH
- 304 M4 Power Domain Configuration
- 304 M4 Power Domain Status
- 304 M4 Entering Low Power Mode
- 304 M4 Exiting Low Power Mode
- 304 M4 SRAM Power Domain Configuration
- 304 M4 SRAM Power Domain Status
- 304 M4 SRAM Entering Low Power Mode
- 305 M4 SRAM Exiting Low Power Mode
- 305 Voice (Audio) Sub-System Low Power Modes
- 305 Entry to a Low Power State
- 305 Exiting from a Low Power State
- 305 Voice (Audio) Sub-System SRAM Low Power Modes
- 305 Entry to a Low Power State
- 305 Exiting a Low Power State
- 305 FPGA (FB) Sub-System Low Power Modes
- 307 Sensor Processing (FFE) Sub-System Low Power Modes
- 307 SDMA Low Power Mode
- 308 THE CONFIGURATION MANAGER SUB-SYSTEM
- 308 Introduction
- 308 Configuration sub-system architecture
- 309 Configuration State Machine General Operation
- 309 Read Header Contents from Flash
- 310 Boot SPI
- 310 Deep Sleep Mode
- 310 Software Considerations
- 311 Configuration DMA
- 312 How to Start a DMA
- 312 How to Stop an Active DMA Transfer
- 313 SPI MASTER
- 314 SPI Master
- 314 SPI Transfer Modes
- 315 Transmit and Receive
- 315 Transmit Only
- 315 Receive Only
- 315 EEPROM Read
- 316 SPI Flash Command Write
- 318 SPI Flash Page Write
- 319 Sytem Clocks
- 319 CLOCK SETUP
- 319 Change the Oscillator Frequency
- 321 Oscillator Programming Table
- 322 Setup the Clock Source
- 325 Setup the Divider
- 333 Enable the Clock Gate
- 339 FUNCTIONAL DOMAIN CLOCK SETUP
- 340 Setup PKFB clocks
- 340 Setup Fabric clocks
- 342 Setup Voice Subsystem clocks
- 342 Setup SDMA clocks
- 343 Setup M4 clocks
- 343 Setup A1 CfgSM Clocks
- 345 Setup Analog-to-Digital Convertor
- 347 Setup I2S Slave Clock
- 350 Setup M4 Peripheral Clocks
- 351 HOW TO BRING CLOCK OUT TO DEBUG PIN
- 353 SOFTWARE RESETS
- 357 TERMINOLOGY AND CONVENTIONS
- 357 Glossary of terms
- 361 Structure of a register definition
- 363 REFERENCE DOCUMENTS