Hardware sources for initiating low-power modes. Qwiic QuickLogic Thing Plus - EOS S3

32.2.2.2

Hardware sources for initiating low-power modes

The following table summarizes for each power domain the hardware sources that can initiate entry to low power mode entry. Some hardware sources are maskable.

Table 32-3: Entering Low Power Modes by Hardware

Power Domain Hardware Source to Enter Low Power Mode

M4

FFE

FB

PF

AD0

AD1

AD2

AD3

AD4

–

FFE BUSY signal falling edge (See Section 0 )

FB Interface falling edge (See Section 32.7

)

FB Interface falling edge (See

–

–

Section 32.7

)

AD5

A1 eFuse

–

–

–

–

–

–

–

I2S

SDMA

–

When SDMA is in idle state longer than

SDMA_BRIDGE.SDMA_PWRDN_CNT (See Section 32.9

)

M4SRAM[15:12] –

M4SRAM[11:0]

PF SRAM

FFE SRAM

M4 SRAM will enter DS mode when M4 enters SD mode † if MEMORY_POWER_DOWN_CONTROL[11:0] = 1

PF SRAM will enter DS mode when PF enters low-power mode if MEMORY_POWER_DOWN_CONTROL[17] = 1

FFE SRAM will enter DS mode when FFE enters low-power mode † if MEMORY_POWER_DOWN_CONTROL[16] = 1

AD1 (Left)

SRAM

AD1 SRAM will enter DS mode when AD1 enters shutdown mode

AD2 (Right)

SRAM

AD2 SRAM will enter DS mode when AD2 enters shutdown mode

SDMA SRAM

SDMA SRAM will enter DS mode when SDMA enters low-power mode

† if MEMORY_POWER_DOWN_CONTROL[18] = 1

† See MEMORY_POWER_DOWN_CONTROL register description for more details.

Maskable?

–

Yes

–

–

–

–

–

–

–

–

Yes

–

–

Yes

–

DS: Yes

DS: Yes

SD: No

DS: Yes

SD: No

No

No

Yes

32.2.3

Methods for exiting Low Power Modes

Each power domain may be taken out of a low power mode by M4 firmware or by the TLC writing to a control bit. Some power domains exit low power mode by PMU hardware through an event.

EOS S3 TRM (r1.01a) Confidential Page 299