Appendix A.

Terminology and Conventions

A.1.

Glossary of terms

The following table explains the terminology, conventions, abbreviations, and acronyms used.

Table: Glossary of Terms

Term

A0N

A1

AD0

AD1

AD2

AD3

AD4

AD5

ADC

AHB

AIP

AON

APB

APC

Bit-banding

Bootstrap pin

CFGSM

Description

Always ON power domain (does not turn off)

Include AP interface (TLC), SYS_RSTn, GPIO,

ADC, PMU, LDO, slave I2S

Configuration DMA, Master SPI

Audio domain 0

Voice sub-system audio DMA power domain/clock

Audio domain 1

Voice sub-system PDM_LEFT power domain/clock

Audio domain 2

Voice sub-system PDM_RIGHT power domain/clock

Audio domain 3

Voice sub-system LPSD power domain/clock

Audio domain 4

Voice sub-system I2S_MASTER power domain/clock

Audio domain 6

Voice sub-system top level (APB I/F) power domain/clock

Analog to Digital Converter

ARM Advanced High-performance Bus – typically this bus is running at high speed.

Modules such as CPU, DSP, co-processors, memory, FIFO, etc. all interface to this bus.

Analog IP block

Always ON power domain or circuit inside AON power domain

ARM Advanced Peripheral Bus – typically “slow” peripheral bus for interface with external devices.

Analog power control, a part of the PMU

Maps a complete word of memory onto a single bit in the bit-band region. to configure the operating (or pin configuration) mode, tie the pin to high (VCCIO) or low (GND) during period when external reset (SYS_RSTN) is asserted .

Configuration State Machine

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Term

CODEC

CfgDMA

CM

Coremark

CoreSight

DBG

DM0, DM1

DMA

DST

DTM

DWT eFuse

Fabric

FB

FBIO

CfgSM

Cortex-M4F

CRU

DAP

FFE

FCLK

FPB

Description

Coder/Decoder – in EOS, CODEC encodes or decodes digital audio signals

Configure DMA module

Configuration State Machine group is made up of the CFG_SM, SPI0_Master, and the CFG_DMA controller for DMA transfer from flash memory through the SPI_Master port

Depends on context, Is either

1) Communication Manager

2) Code memory in FFE

Benchmark standard.

ARM debugging and trace technology. The infrastructure for monitoring, tracing, and debugging a complete system on chip.

ARM deeply embedded processor with floating point arithmetic functionality; low-power, low gate count, low interrupt latency, and low-cost debug

Clock Reset Unit

ARM Debug Access Port – A TAP block that acts as an AMBA, AHB or AHB-Lite, master for access to a system bus. The DAP is the term used to encompass a set of modular blocks that support system wide debug.

Debug Controller

Data memory in FFE

Direct Memory Access

Disable Self Time

ARM M4 Data Watchpoint and Trace – part of the ARM debug architecture

Electronic fuse – options that are factory programmed by QuickLogic

Another name for FPGA

Refers to Fabric (FPGA) module, its power domain, its clock

I/O belonging to the FPGA fabric.

Flexible Fusion Engine module/ power domain/clock

Ultra-low power μDSP-like processor that performs routine tasks

Fast Clock

ARM M4 Flash Patch and Breakpoint – A set of address matching tags, which reroute accesses into flash to a special part of SRAM. This permits patching flash locations for breakpointing and quick fixes or changes.

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MPU

MS0

MS1

MS2

MS3

NVIC

OSC

PCM

PDM

PF

PIF

PKFB

PMU

PMUT

POR

RTC

SCS

SDMA

SM

SM0, SM1

Term

FPU

HSO

I2S

ITM

JTM

Light Sleep

LPMF

LPMH

LPSD

Description

Floating Point Unit

High Speed Oscillator

Inter IC Sound

ARM Instrumentation Trace Macrocell – part of the ARM debug architecture

Delta-Sigma ADC

SRAM low power mode with lower leakage advantage but access time penalty.

SRAM (Footer) circuit to enable light sleep mode.

SRAM (Header) circuit to enable deep sleep mode.

Low Power Sound Detect (acoustic activity detection IP from Sensory Inc. )

For information refer to http://www.sensory.com/

Memory Protection Unit – hardware to protect region of memory

M4 SRAM Instance M4S0–M4S3 power domain/clock

M4 SRAM Instance M4S4–M4S7 power domain/clock

M4 SRAM Instance M4S8–M4S11 power domain/clock

M4 SRAM Instance M4S12–M4S15 power domain/clock

Nested Vectored Interrupt Controller – Provides the M4F processor with configurable interrupt handling abilities.

Oscillator

Pulse Code Modulation – for digital audio in EOS

Pulse Density Modulation – for digital audio in

EOS

Packet FIFO module/ power domain/clock

FPGA Programming Interface

Packet FIFO Bank

Power Management Unit

Power Management Unit Timer – simple periodic timer power-on reset

Real-Time Clock (not calendar)

The ARMv7-M System Control Space

System DMA

The term SM is used in some register descriptions to denote sensor memory.

Sensor Manager - there are two in the S3

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Term

SPI

Description

Serial Peripheral Interface – synchronous serial interface with separate clock and unidirectional data signals and chip select. A SPI module is either master (generates clock) or slave

(receives clock). There are three SPI modules in the S3.

SPI_0_Master The SPI interface in the Sensor Processor

SPI_1_Master

The SPI interface used to load data from external flash memory

SPI_1_Slave

SPT

STM

The SPI interface in the Communications

Manager block, used to communicate with an

Application Processor host..

Simple Periodic Timer

Generates 1ms interval counter; requires count error compensation for accuracy.

Software Test Mode – pin used to enter test mode

ARM Serial-Wire Debug Port – An optional external interface for the DAP that provides a serial-wire bidirectional debug interface.

SW-DP, also known as

SWD

SWV

TAP

Serial-Wire Viewer. Debug tool.

Test Access Port – The collection of four mandatory and one optional terminal that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI , TDO , TMS , and TCK . The optional terminal is TRST . This signal is mandatory in ARM cores because it is used to reset the debug logic.

Also known as the M4 Timer Timer1

TLC

TLS

TPA

TPIU

Top Level Controller

Transparent Light Sleep – SRAM low power mode; lower pro: leakage, con: performance penalty to get in/out of TLS mode.

ARM Trace Port Analyzer – A hardware device that captures trace information output on a trace port. This can be a low-cost product designed specifically for trace acquisition, or a logic analyzer.

ARM M4 Trace Port Interface Unit – part of the

ARM debug architecture

VoiceQ

VoiceQ is a voice sensing technology by Knowles

Corporation http://www.knowles.com/ wake-up interrupt controller WIC

Wishbone bus An SoC IP interconnect bus

WU wake-up

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