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36.2
Setup PKFB clocks
The PacketFifo (PKFB) typically receives data from FFE, so PKFB clock enabling is very similar to FFE. PKFB’s maximum frequency is 10 MHz
Important: Remember that PKFB Power domain needs to be powered up before enabling the clocks. By default, the PKFB power domain is SHUTDOWN out of reset.
1.
Setup the Clock Source. Typically, the High-Speed OSC is selected as source. a.
C01 - CLK_Control_A_1 (0x004) = 2’b00 ( default ) b.
C08 – CLK_SWITCH_FOR_C (0x134) = 1’b0 ( default )
2.
Setup the Divider a.
C01 – CLK_Control_A_0 (0x000) and C01_CLK_DIV (0x110).
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Note that CLK_Control_A_0 impacts C10 frequency, and C01 is a divided down clock from C10. b.
C08_X4 – CLK_Control_C_0 (0x010)
•
C08_X1 is divided down by 4 from C08_X4. This is fixed.
3.
Enable the Clock Gate a.
C01_CLK_GATE (0x040) [2] = 1. E b.
C08_X1_CLK_GATE (0x04C)[3] = 1.
Note E: If using SPT periodic timer to wake FFE periodically, then SPT clock gate needs to be enabled. Set
C01_CLK_GATE[9] =1 too.
SPI slave interface can also pop data from PKFB. SPI clock is from C00 – PAD16, and has a maximum frequency of 20 MHz.
Fabric can also push data into PKFB, which requires C41 to be configured into fabric design.
36.3
Setup Fabric clocks
Fabric (FB) is on-chip configurable logic. FB can configured with different designs once powered up. Once FB is powered down, or chip reset is applied, that design is lost and needs to reconfigure again.
Important: Remember that Fabric Power domain needs to be powered up before enabling the clocks. By default, the Fabric power domain is SHUTDOWN out of reset. Please refer to EOS S3 Power Management User
Guide for details on how to power Fabric domain on.
Fabric (FB) has 3 inputs clocks. These input clocks are used to drive various FPGA designs as needed. This is dependent on the actual design configured and loaded into Fabric.
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C16 - Sys_Clk0
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C21 - Sys_Clk1
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C02 - Sys_Pclk
Also Fabric has 2 output clocks. These output clocks go from Fabric into the SOC. These clocks drive specific logic within the EOS S3.
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C40 (Fabric to Wishbone clock) – WB_CLK
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C41 (Fabric to PKFB clock) – Sys_Pkfb_Clk
C40 requires Wishbone Slave design loaded into Fabric. This clock drives the Wishbone interface, which allows M4 to write/read the Fabric via that interface. The maximum frequency of this clock is 10 MHz
EOS S3 TRM (r1.01a) Confidential Page 340
C41 requires the fabric design which pushes data into the PacketFifo. This clock drives the Fabric to PKFB interface. The maximum frequency of this clock is 10 MHz. Note: Remember to turn off C41 before powering down PacketFifo domain.
Important: C40/C41 is NOT output clock to EOS S3 PADS. General Fabric IO can be configured instead to be an output clock to PAD if needed.
M4 can write Fabric via an AHB to Wishbone Bridge. The Fabric requires to be configured with a fabric design with Wishbone slave design to generate C40.
Enable the Fabric Configuration clocks:
1.
Power up the Fabric domain. Please refer to EOS S3 Power Management User Guide.
2.
Program divider and clock gate for C09 a.
C09_CLK_DIV (0x114) – Divider and root clock gate for C09.
3.
Enable the clock gates a.
C09_CLK_GATE(0x118) = 0x6.
Once the Fabric is configured, enable the Fabric input clocks:
1.
Program the dividers and clocks source for fabric input clocks as desired. a.
C16 – CLK_Control_F_0 (0x020) / CLK_Control_F_1 (0x024). b.
C21 – CLK_Control_I_0 (0x034) / CLK_Control_F_1 (0x038). c.
C02 – CLK_Control_B_0 (0x008) / CLK_Control_B_1 (0x00C).
2.
Enable the Clock Gates a.
Ensure that CLK_DIVIDER_CLK_GATING(0x0124) [1] (C02) ,[5] (C16) , [8] (C21) are all set to
1. This is the master clock gate going into each divider (B, F, I). b.
C16_CLK_GATE(0x0x64)[0] = 1 to enable Sys_Clk0. c.
C21_CLK_GATE(0x070)[0] = 1 to enable Sys_Clk1. d.
C02_CLK_GATE (0x044) [1] = 1 to enable Sys_Pclk.
EOS S3 TRM (r1.01a) Confidential Page 341
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