SYSTEM BUSES. Qwiic QuickLogic Thing Plus - EOS S3

Chapter 4.

System Buses

4.1

M4 AHB bus

In power domain: M4

The M4 AHB bus is one of two AHB buses in the S3. It is a 32-bit bus operating at 80 MHz.

The M4 AHB bus connects to the system elements shown in Figure 2-1

4.2

AON AHB bus

In power domain: A0 (always on)

The AHB AON bus is one of two AHB buses in the S3. It is a 32-bit bus operating at 10 MHz.

The AHB AON bus connects to the system elements shown in Figure 2-1.

4.3

AHB2APB bus bridges

There are four separate AHB2APB bus bridges, connecting the AHB buses to APB peripherals.

They are:

Bridge #

AHB2APB bridge 0

AHB2APB bridge 1

AHB2APB bridge 2

AHB2APB bridge 3

Power domain

M4

M4

AON

AON

Bridge to these modules:

UART, Watchdog timer, and Timer1 for M4

Voice / audio processor sub-system eFuse

I2S slave, SDMA

EOS S3 TRM (r1.01a) Confidential Page 58