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The following PIDs and CIDs are from ARM Cortex-M4 TRM 3 .
Table 3-7: ROM Table ID values: Peripheral IDs, Component IDs and derived values (from ARM)
Offset
0xFD0
0xFD4
0xFD8
0xFDC
0xFE0
0xFE4
0xFE8
0xFEC
0xFF0
0xFF4
0xFF8
0xFFC
Name
PID4
PID5
PID6
PID7
PID0
PID1
PID2
PID3
CID0
CID1
CID2
CID3
Base Address: 0xE000_0xxx 0xE000_2xxx 0xE004_0xxx 0xE000_Exxx 0xE00F_Fxxx
Description ITM FPB TPIU SCS Coresight DAP
Peripheral ID 4
Peripheral ID 5
Peripheral ID 6
Peripheral ID 7
Peripheral ID 0
Peripheral ID 1
Peripheral ID 2
Peripheral ID 3
Component ID 0
Component ID 1
Component ID 2
Component ID 3
0x04
0x00
0x00
0x00
0x01
0xB0
0x3B
0x00
0x0D
0xE0
0x05
0xB1
0x04
0x00
0x00
0x00
0x03
0xB0
0x2B
0x00
0x0D
0x04
0x00
0x00
0x00
0xA1
0xB9
0x0B
0x00
0x0D
0x04
0x0C†
0xB0
0x0B
0x00
0x0D
0x04
0x00
0x00
0x00
0xC4
0xB4
0x0B
0x00
0x0D
Part Number (PID1[3:0],PID0[7:0)) 0x001
Designer (JEDEC) ID (PID2[6:4],PID1[7:4]) 0x3B
Revision (PID2[7:4]) 0x3
ECO Revision (PID3[7:4]) 0x0
Customer modification number (PID3[3:0]) 0x0
Note:
Component ID (CID3,CID2,CID1,CID0)
0xB105_E00
D
0xE0
0x05
0xB1
0x003
0x3B
0x2
0x0
0x0
0xB105_E00
D
0x90
0x05
0xB1
0x9A1
0x3B
0x0
0x0
0x0
0xB105_900
D
0xE0
0x05
0xB1
0x00C
0x3B
0x0
0x0
0x0
0xB105_E00
D
0x10
0x05
0xB1
0x4C4
0x3B
0x0
0x0
0x0
0xB105_100
D
† SCS CoreSight part number = 0x000 if no FPU, 0x00C if FPU present
3.4.2
CPUID register
CPUID register is at 0xE000_ED00. The value should be 0x410F_C240 (from ARM DDI0439B)
Table 3-8: CPUID Register Bit Description
0xD00 CPUID
IMPLEMENTER
VARIANT
CONSTANT
PARTNO
REVISION bit R/W/C Default Description
31:24 RO
23:20 RO
19:16 RO
15:4
3:0
RO
RO
0x41
0x0
0xF
Implementer: 0x41 = ARM
Processor revision: 0x0 = Rev 0
Read as 0xF
0xC24 Part number: 0xC24 = Cortex-M4
0x0 Patch release: 0x0 = Patch 0
3 ARM DDI0439B Cortex-M4, r0p0, TRM
EOS S3 TRM (r1.01a) Confidential Page 36
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