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14.5.2
Transfer Types
There are three basic transfer types. These are:
•
Transfers to TLC local registers
These transfers access TLC local registers alone and do not produce any activity on the AHB interface.
•
Transfers from Packet FIFOs.
These transfers also access the TLC local registers. However, the goal of these accesses is to read one or more bytes from the Packet FIFOs.
These read transactions can be conducted as a single or burst transfer.
•
Transfers to resources in the M4 Memory address space.
These transfers also access the TLC local registers. However, the goal of these accesses is to conduct a transfer using the AHB interface.
These transfers provide for the following operations:
Single, 4-byte read transfers to the M4’s Memory space.
Burst write transfers to the M4’s Memory space.
Burst read transfers from the M4’s Memory space.
14.5.2.1
Transfers to TLC Local Registers
These transfers will depend upon the type of TLC register being accessed. The default TLC response is to automatically increment the TLC register address (not the M4 Memory space address) after each byte access.
An example would be a read from the M4 Memory Address registers. The SPI protocol’s address phase will use the address for the “Memory Address Byte 0” register. Once this transfer has completed, the TLC will then automatically increment its register address to “Memory Address Byte 1”. Similarly, once this transfer has completed, the TLC will then automatically increment its register address to “Memory Address Byte 2”. This sequence will repeat until all bytes have been transferred or a TLC register address is reached that prevents this auto-incrementing operation. TLC register types that prevent auto-incrementing will be discussed in later sections.
It is also important to note that this auto-incrementing operation does not prevent any special features in these registers from being triggered. For example, writes to “Memory Address Byte 1” may cause a value to automatically be read from the M4 Memory space. A later section will discuss this transfer in more detail.
14.5.2.2
Transfers from Packet FIFOs
Packet FIFOs accessible from within TLC can only be read and not written. Therefore, writes to the Packet
FIFOs are ignored. Conversely, since these are FIFOs, a burst read from these FIFOs requires that the same
TLC register address be accessed multiple times. For this reason, the TLC does not increment its register address when accessing any Packet FIFO address.
14.5.2.3
Transfers to M4 Memory Address Space
The following sections will outline the transfer types and restrictions when accessing the M4’s Memory
Address space through the AHB Bridge interface.
14.5.3
Basic AHB Transfer Restrictions
The TLC restricts AHB Memory transfers to 4 bytes per transfer cycle. No other transfer size is currently supported. The following sections will expand on additional transfer specific restrictions.
EOS S3 TRM (r1.01a) Confidential Page 118
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