Functional Description. Qwiic QuickLogic Thing Plus - EOS S3

27.2.2

Functional Description

27.2.2.1

Logic Cell

Each logic cell is a multiplexer-based single register. The cell has a high fan-in, and fits a wide range of functions with up to 22 simultaneous inputs (including register control lines), and four outputs (three combinatorial and one registered). Figure 27-1 , Logic Cell Block Diagram , illustrates the logic block structure.

The high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay. The logic cell can implement the following functions:

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Two independent 3-input functions

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Any 4-input function

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8 to 1 mux function

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Independent 2 to 1 mux function

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Inverted or non-inverted clock signal to flip-flop

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Single dedicated register with active high clock enable, set and reset signals

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Direct input selection to the register, which allows combinatorial and register logic to be used separately

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Combinatorial logic can also be configured as an edge-triggered master-slave D flip-flop

EOS S3 TRM (r1.01a)

Figure 27-1: Logic Cell Block Diagram

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