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3.6.2
Memory Address Decoding
The following table summarizes the Cortex-M4-F memory address decoding.
Table 3-13: Memory Address Decoding Table (with reference to Excel tab)
Block
M4_mem0
M4_mem1
M4_mem2
M4_mem3_aon
RESERVED (code address space)
M4_mem0 (Mirror)
M4_mem1 (Mirror)
M4_mem2 (Mirror)
M4_mem3_aon (Mirror)
RESERVED (SRAM address space)
M4_Regs
Packet FIFO Bank
Clock
PMU - Power Management Unit
Intr_Ctrl (WIC)
IO_Mux
Misc
AIP (Analog IP includes RTC, OSC, and
LDO)
RESERVED
JTM (ADC)
SPT (RTC)
RESERVED
A1_Regs
SPI_MS
DMA_SPI_MS eFuse
RESERVED
I2S_Slave
SDMA
SDMA_Bridge
–
–
–
–
[this column reserved for future use]
M4 Base
Address
Last Address Size †
0x0000_0000
0x0002_0000
0x0004_0000
0x0006_0000
128KB
128KB
128KB
128KB
0x0008_0000 0x1FFF_FFFF –
0x2000_0000 128KB
0x2002_0000 128KB
0x2004_0000
0x2006_0000
0x2008_0000 0x3FFF_FFFF –
128KB
128KB
0x4000_0000
0x4000_2000
0x4000_4000
0x4000_4400
0x4000_4800
0x4000_4C00
0x4000_5000
4KB
8KB
1KB
1KB
1KB
1KB
1KB
0x4000_5400 1KB
0x4000_5800 0x4000_59FF
0x4000_5A00
0x4000_5C00
0x4000_5E00
–
512
512
–
0x4000_6000
0x4000_7000
0x4000_7400
0x4000_8000
0x4000_9000 0x4000_AFFF –
4KB
1KB
1KB
4KB
0x4000_B000
0x4000_C000
0x4000_D000
4KB
4KB
4KB
EOS S3 TRM (r1.01a) Confidential Page 41
Block
SDMA_SRAM
UART
WDT
Timer
CFG_CTL_TOP (PIF Controller)
AUD_Slave
RAMFIFO0 (FPGA)
RAMFIFO1 (FPGA)
RAMFIFO2 (FPGA)
RAMFIFO3 (FPGA)
Fabric (FPGA)
FFE
DM0 (data memory)
SM0 (sensor manager)
SM1(sensor manager)
ExtRegsFFE
CM (COMM MGR)
RESERVED (peripheral address space)
RESERVED
M4_ITM
Instrumentation Trace Macrocell
M4_DWT
Data Watchpoint Unit
M4_FPB
Flash Patch and Breakpoint
Reserved
[this column reserved for future use]
M4 Base
Address
Last Address Size †
0x4000_F000
0x4001_0000
0x4001_2000
0x4001_3000
0x4001_4000
0x4001_5000
0x4001_8000
0x4001_9000
0x4001_A000
0x4001_B000
0x4002_0000
4KB
4KB
4KB
128KB
0x4004_0000 0x4004_FFFF 128KB
_0000
_4000
_8000
16KB
16KB
8KB
_A000 8KB
0x4005_0000 0x4007_FFFF 192KB
0x4008_0000 0x5FFF_FFFF –
0x6000_0000 0xDFFF_FFFF –
4KB
4KB
4KB
4KB
4KB
4KB
4KB
0xE000_0000 0xE0000_0FFF 4KB
0xE000_1000 0xE0000_1FFF 4KB
0xE000_2000 0xE0000_2FFF 4KB
0xE000_3000 0xE000_DFFF –
EOS S3 TRM (r1.01a) Confidential Page 42
Block
[this column reserved for future use]
M4 Base
Address
Last Address Size †
M4_SCS
System Control Space
Interrupt Controller Type (ICTR) and
Auxiliary Control Registers (ACTLR)
SysTick
Reserved
M4_NVIC
Nested Vectored Interrupt Controller
Reserved
M4_CPUID ‡
Misc SCS Registers
M4_MPU
Reserved
Misc SCS Registers
M4_FPU
Reserved
–
SCS
0xE000_E000 0xE000_EFFF 4KB
0xE000_E000 0xE000_E00F –
0xE000_E010 0xE000_E01F –
0xE000_E020 0xE000_E0FF –
0xE000_E100
0xE000_E200
0xE000_E300
0xE000_E400
0xE000_E500 0xE000_ECFF –
0xE000_ED00 0xE000_ED03 –
0xE000_ED04 0xE000_ED8F –
0xE000_ED90 0xE000_EDFF –
0xE000_EE00 0xE000_EEFF –
0xE000_EF00 0xE000_EF33 –
0xE000_EF34 0xE000_EF47 –
0xE000_EF48 0xE000_EFCF
M4_SCS ID registers ^ 0xE000_EFD0 0xE000_EFFF –
Reserved
M4_TPIU
Trace Port Interface Unit
Reserved
M4_DAP
Debug Access Port
0xE000_F000 0xE003_FFFF –
0xE004_0000 0xE004_0FFF –
0xE005_0000 0xE00F_EFFF –
0xE00F_F000 0xE00F_FFFF –
Vendor_SYS: not used
Notes:
0xE010_0000 0xFFFF_FFFF –
•
See ARM TRM for details for ARM IP block
‡ CPUID described in Section Cortex M4-F Core Peripherals
^ ID registers described in Section M4-F sleep mode
EOS S3 TRM (r1.01a) Confidential Page 43
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