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36.9
Setup I2S Slave Clock
I2S Slave clock receives its input clock (C32) from PAD 31. Remember that the
IOMUX_PAD_31_CTRL/IOMUX_I2S_WD_CLK_IN_SEL needs to configure to receive clock on PAD31. The maximum frequency of C32 is 10 MHz. Also, the I2S is configured by C01. Below is the procedure to enable the I2S clocks.
1.
Setup the Clock Source as OSC a.
CLK_Control_A_1 (0x004)= 2’b00 ( default )
2.
Setup the Divider a.
CLK_Control_A_0 (0x000)
3.
Enable the Clock Gates a.
C01_CLK_GATE(0x040)[5] = 1 enables the APB configuration clock to I2S.
4.
Setup the IOMUX to allow C32 as input from PAD31 a.
IOMUX_PAD_31_CTRL = 0x220. See
EOS S3 TRM (r1.01a) Confidential Page 347
b.
Table 36-3: IOMUX_PAD_32_CTRL Register below. c.
IOMUX_I2S_WD_CLKIN_SEL = 1. Table 36-4: IOMUX_I2S_WD_CLKIN_SEL Register
EOS S3 TRM (r1.01a) Confidential Page 348
Table 36-3: IOMUX_PAD_32_CTRL Register
Address Register Name
0x40004C7C IOMUX_PAD_31_CTRL
Bit Field
31:0
R/W
Access
PAD_31_FUNC_SEL
PAD_31_CTRL_SEL
PAD_31_OEN
1:0
4:3
5
RW
RW
RW
Default Description
0x0
0x0
0x1
Functional selection for IO output
Refer to IO Mux
Control selection for IO output
0x0 = A0 registers (as defined below)
0x1 = Others
0x2 = Fabric
Active low output enable
0x1: driver disabled
0x0: normal operation
PAD_31_P 7:6 RW 0x0
Driver state control
0x0: Z
0x1: pull up
0x2: pull down
0x3: keeper
PAD_31_E
PAD_31_SR
PAD_31_REN
I2S_WD_CLKIN_SEL
9:8
10
11
0
RW
RW
RW
RW
0x1
0x0
0x0
0x0
Drive Strength
0x0: 2mA
0x1: 4mA
0x2: 8mA
0x3: 12mA
Slew Rate
0x1: Fast
0x0: Slow (half frequency)
Receive enable
0x1: enable
0x0: disable
Schmitt Trigger
0x1: enable
0x0: disable PAD_31_SMT 12
Table 36-4: IOMUX_I2S_WD_CLKIN_SEL Register
Address Register Name
0x40004DA0 IOMUX_I2S_WD_CLKIN_SEL
Bit
Field
31:0
RW
R/W
Access
0x0
Default Description
Sel
0: 0
1: pad #23
EOS S3 TRM (r1.01a) Confidential Page 349
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