FPGA main modules. Qwiic QuickLogic Thing Plus - EOS S3

2.3.4

FPGA main modules

This sub-system includes the FPGA, its configuration module, and internal RAM, The FPGA provides userconfigurable glue logic and a small amount of storage. See Chapter 27 for details.

2.3.5

Communication Manager Modules

This sub-system includes the SPI_Slave interface for use with a Host; the TLC, and the DMA for the CM.

2.4

Buses in the S3: AHB, secondary buses, and bridges

The S3 bus hierarchy is designed to support optimum functional partitioning with power management in mind. The hierarchy allows the S3 the ability to support system power at fine granularity.

Main buses

There are two AHB buses in the S3: the M4 AHB which is tightly coupled to the M4 processor and which is in the same power domain, and the AON AHB which is always on.

Each AHB bus has several bus bridges attached to it to connect to various APB modules. These allow separating the high-speed core from slower elements, aiding power savings capability

Bridges between main buses

The AHB2AHB Bridge 0 connects the M4 AHB bus to the AON AHB bus, which is always on. This allows independent power operation of the AHB buses. This bridge also connects to the Ext M4 reg block.

The AHB2AHB Bridge 1 connects the M4 AHB bus to the AON AHB bus but also supports connection to SRAM.

Secondary bridges from buses

The secondary bridges are:

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AHB2APB Bridge 0 supports smaller modules like the UART and some timers.

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AHB2APB Bridge 1 mainly supports the Voice / audio processor sub-system.

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AHB2APB Bridge 2 supports the eFuse system component which is for factory use.

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AHB2APB bridge 3 supports SDMA and the I2S slave module.

EOS S3 TRM (r1.01a)