FPGA Sub-system

Chapter 27.

FPGA sub-system

27.1

Introduction

This sub system provides capability to add logic for custom operating functions.

Configuration for 2400 effective logic cells is stored in 64 Kbit SRAM.

27.1.1

Power

Power Domain: FPGA

27.2

Sub-system Architecture

The on-chip programmable logic provides flexibility to the EOS S3 platform for implementing additional, customer-determined, functions. The logic block consists of multiplexor based logic cells, built-in RAM modules and FIFO controllers, built-in multipliers, as well as pre-built interfaces with I/O drivers of the EOS

S3 device. Key functionality is listed in the following table.

Table 27-1: On-Chip Programmable Logic Major Features

Feature

Logic Cells

8K RAM Modules

(9,216 bits)

FIFO Controllers

RAM Bits

Configurable

Interface

Multiplier

Parameters

891

8

8

65,536

32

2x 32 x 32 (or 4x 16 x 16)

27.2.1

FPGA sub-system components

•

Configuration Memory

•

Configuration controller - [description to be added]

•

Configurable logic matrix

•

Bus Interface

•

Eight RAM FIFO Controllers

EOS S3 TRM (r1.01a) Confidential Page 261