Nested Vectored Interrupt Controller (NVIC). Qwiic QuickLogic Thing Plus - EOS S3

3.8

Nested Vectored Interrupt Controller (NVIC)

In power domain: M4

The Nested Vectored Interrupt Controller (NVIC) is closely integrated with the processor core to achieve low latency interrupt processing. The system design includes the Wake Up Interrupt controller which can stay on while the processor and NVIC can be put into a very low-power sleep mode, leaving the WIC to identify and prioritize interrupts and awaken items in the CPU power domain.

NVIC Features include:

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25 External interrupts

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8 levels of priority

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Dynamic reprioritization of interrupts.

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Priority grouping. This enables selection of preempting interrupt levels and non-preempting interrupt levels.

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Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts.

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Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead.

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QuickLogic has integrated the NVIC operation with the Wake-up Interrupt Controller (WIC) module, providing ultra-low power sleep mode support where the WIC, through the PMU, can wake up a ARM core from sleep state.

The location of the NVIC in the system architecture is shown in figure below.

EOS S3 TRM (r1.01a)

Figure 3-4: NVIC in S3 system architecture

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