advertisement
28.2.5
DAP accessible ROM table
The Debug Access Port (DAP)-accessible ROM table is defined as follows:
Base address=0xE00F_F000
Table 28-1: ARMv7-M DAP accessible ROM table
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
Value
0xFFF0_F003
0xFFF0_2003
0xFFF0_3003
0xFFF0_1003
0xFFF4_1003
0xFFF4_2002
0x0000_0000
Name
ROMSCS
ROMDWT
ROMFPB
ROMITM
ROMTPIU rometm
END
Description
Points to the SCS at 0xE000_E000
Points to the DWT at 0xE000_1000
Points to the FPB at 0xE000_2000
Points to the ITM at 0xE000_0000
Points to the TPIU at 0xE004_0000
Points to the ETM at 0xE000_1000 (not fitted, thus last nibble = 2)
End of table marker of 0x0000_0000
The value in the table (except the last nibble) is a negative pointer relative to ROM table base address of
0xE00F_F000 . The last nibble = 2 if the feature is not fitted; = 3 if the feature is fitted.
For example ROMITM has value of 0xFFF0_1003. Drop the last nibble and take 2’s complement:
2’s complement of 0xFFF0_1000 = 0x000F_F000
Then subtract from ROM table base address
0xE00F_F000 – 0x000F_F000 = 0xE000_0000
The ITM is located at 0xE000_0000. See section 28.3 for details.
28.2.6
AHB-AP
The AHB-AP is a Memory Access Port (MEM-AP) component of the Debug Access Port (DAP) as defined in the
ARM Debug Interface v5 Architecture Specification 5 . The AHB-AP is a debug access port into the Cortex-M4 system, and provides access to all memory and registers in the system, including processor registers through the SCS. System access is independent of the processor status. SW-DP is used to access the AHB-AP.
The AHB-AP is a master into the Bus Matrix. Transactions are made using the AHB-AP programmer’s model, which generates AHB-Lite transactions into the Bus Matrix.
28.3
Instrumentation Trace Macrocell (ITM)
The Instrumentation Trace Macrocell (ITM) provides a memory-mapped register interface to allow applications to write logging / event words to the external Trace Port Interface Unit (TPIU). The ITM also supports control and generation of timestamp information packets. The event words and timestamp information are formed into packets and multiplexed with hardware event packets from the Data Watchpoint and Trace (DWT) block according to the packet protocol described in ARM®v7-M Architecture Reference
Manual .
28.3.1
ITM Registers
There are 32 stimulus source ports and 3 control/status registers for total of 35 registers in ITM.
Base address = 0xE000_0000
5 ARM IHI0031x ARM Debug Interface (ADI)
EOS S3 TRM (r1.01a) Confidential Page 279
Table 28-2: ITM Registers
STIM15
STIM16
STIM17
STIM18
STIM19
STIM20
STIM21
STIM22
STIM23
STIM24
STIM25
STIM26
STIM27
STIM0
STIM1
STIM2
STIM3
STIM4
STIM5
STIM6
STIM7
STIM8
STIM9
STIM10
STIM11
STIM12
STIM13
STIM14
STIM28
STIM29
STIM30
STIM31
Address
Offset
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
0x060
0x064
0x068
0x06C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x070
0x074
0x078
0x07C
0XE00
0xE40
0xE80
Name
TER
TPR
TCR
Description
Trace enable register
Trace privilege register
Trace control register
Refer to ARM®v7-M Architecture Reference Manual for more details.
Stimulus port register 0
Stimulus port register 1
Stimulus port register 2
Stimulus port register 3
Stimulus port register 4
Stimulus port register 5
Stimulus port register 6
Stimulus port register 7
Stimulus port register 8
Stimulus port register 9
Stimulus port register 10
Stimulus port register 11
Stimulus port register 12
Stimulus port register 13
Stimulus port register 14
Stimulus port register 15
Stimulus port register 16
Stimulus port register 17
Stimulus port register 18
Stimulus port register 19
Stimulus port register 20
Stimulus port register 21
Stimulus port register 22
Stimulus port register 23
Stimulus port register 24
Stimulus port register 25
Stimulus port register 26
Stimulus port register 27
Stimulus port register 28
Stimulus port register 29
Stimulus port register 30
Stimulus port register 31
EOS S3 TRM (r1.01a) Confidential Page 280
advertisement