Timers. Qwiic QuickLogic Thing Plus - EOS S3

3.9

Timers

3.9.1

M4 Timer

Power domain: M4

The M4 Timer is also known as Timer1. It is in the M4 power domain. For a timer in a separately controlled power domain, refer to the SPT.

The M4 Timer is a 32-bit down counter connected to the M4 APB and it has the following features:

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Generates an interrupt request signal, TIMERINT, when the counter reaches 0. The interrupt request is held until it is cleared by writing to the INTCLEAR Register.

•

Uses the zero to one transition of the external input signal, EXTIN, as a timer enable.

•

If the APB timer count reaches 0 and, at the same time, the software clears a previous interrupt status, the interrupt status is set to 1.

The external clock, EXTIN, must be slower than half of the peripheral clock because it is sampled by a double flip-flop and then goes through edge-detection logic when the external inputs act as a clock.

The following diagram illustrates the M4 Timer block architecture.

EOS S3 TRM (r1.01a)

Figure 3-5: M4 Timer Block Diagram

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