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Chapter 17.
Analog IP (AIP) block
The Analog IP block consists of the RTC, OSC, and LDO modules. Items in this block relate to control of oscillators, timers, or DC voltage regulators.
17.1
Real time clock discussion to be added
For RTC registers, see Section 17.5.
17.2
HS_OSC discussion to be added
17.3
APC discussion to be added
17.4
LDO discussion to be added
17.5
AIP group registers
Base address = 0x4000_5400
Table 17-1: RTC_CTRL_1 Register
0x004 RTC_CTRL_1
Bit Field
RESERVED
31:0 bit
31:5
R/W/C Default Description
5'b00000 : 32.768 Khz CLKDIV 4:0 RW 0x0
Table 17-2: RTC_CTRL_2 Register
0x008 RTC_CTRL_2
Bit Field
RESERVED
31:0 bit
31:1
R/W/C Default
TEST_CTRL
BYP16K
CLKE
2
1
0
RW
RW
RW
0x0
0x0
0x1
Description
RTC test[4:3] control for rtc bypass mode
0: test[4:3] will be forced to 2'b11 when pad8 is strapped to 1, and forced to 2'b00 when pad8 is strapped to 0
1: normal mode; test[4:0] controlled from 0x1C
Changes internal clock division for 16384 Hz bypass compatibility
1'b0 : xtal is 32KHz
1'b1 : xtal is 16KHz
1'b1 RTC Clock Output Enable
(No SYNC Needed)
EOS S3 TRM (r1.01a) Confidential Page 144
Table 17-3: RTC_CTRL_3 Register
0x00C RTC_CTRL_3
Bit Field
RESERVED
31:0 bit
31:3
CE 2:0
Table 17-4: RTC_CTRL_4 Register
0x010 RTC_CTRL_4
Bit Field
RESERVED
31:0 bit
31:1
WR 0
R/W/C Default
RW 0x0
R/W/C Default
RW 0x0
Table 17-5: RTC_CTRL_5Register
0x014 RTC_CTRL_5
Bit Field
RESERVED
C
31:0 bit
31:1
0
R/W/C
RW
Default
0x0
Table 17-6: RTC_CTRL_6 Register
0x018 RTC_CTRL_6
Bit Field
31:0 bit
PI 31:0
R/W/C
RW 0x0
Default
Table 17-7: RTC_CTRL_7 Register
0x01C RTC_CTRL_7
Bit Field
RESERVED
TEST
31:0 bit
31:5
4:0
R/W/C
RW 0x0
Default
Table 17-8: RTC_STA_0 Register
0x020 RTC_STA_0
Bit Field
RESERVED
31:0 bit
31:4
R/W/C Default oscok 3 RHW 0x0 digtestbus testreq alarm
2
1
0
RHW
RHW
RHW
0x0
0x0
0x0
Description
3'b000 Normal Function
Please refer RTC datasheet for detail
Description
Write Pulse to program the RTC internal Register
Please refer RTC datasheet for detail
Serial Input Clock
Description
Description
Parallel Input data
Please refer RTC datasheet for detail
Description
Please refer RTC datasheet for detail
Description
Please refer RTC datasheet for detail, NO SYNC, FW needs to read it twice to ensure the value.
Please refer RTC datasheet for detail, NO SYNC, FW needs to read it twice to ensure the value.
Please refer RTC datasheet for detail, NO SYNC, FW needs to read it twice to ensure the value.
Please refer RTC datasheet for detail, NO SYNC, FW needs to read it twice to ensure the value.
EOS S3 TRM (r1.01a) Confidential Page 145
Table 17-9: RTC_STA_1 Register
0x024 RTC_STA_1
Bit Field
31:0 bit
PO 31:0
R/W/C
RHW
Default
0x0
Description
Please refer RTC datasheet for detail, NO SYNC, FW needs to read it twice to ensure the value.
Table 17-10: Oscillator Control 0 Register Bit Description
0x080 OSC_CTRL_0
Bit Field
RESERVED
FREF16K_SEL
EN
31:0 bit
31:1
1
0
R/W/C
RW
RW
Default
0x0
0x1
Description
1'b0 : reference clock is 32KHz
1'b1 : reference clock is 16KHz
1'b0 : OSC OFF
1'b1 : OSC ON
(NO SYNC needed, OSC guarantee there is no Glitch)
Table 17-11: Oscillator Control 1 Register Bit Description
0x084 OSC_CTRL_1
Bit Field
31:0 bit
RESERVED 31:16
GENERAL_PURPOS_SFR 15:13
PROG 12:0
R/W/C
RW
Default
0x00
RW 0x92D
Description
Please refer OSC datasheet for others
(No SYNC Needed)
Power On Default Value is 76.97 MHz
No Support on "Delta Mode"
Note:
Default value of 0x92D = 2349 decimal. 32768 Hz × 2349 = 76 972 032 Hz or 76.97 MHz
Table 17-12: OSC_CTRL_2 Register
0x088 OSC_CTRL_2
Bit Field
RESERVED
31:0 bit
31:1
DELTA 0
Table 17-13: OSC_CTRL_3 Register
0x08C OSC_CTRL_3
Bit Field
RESERVED
31:0 bit
31:8
GENERAL_PURPOS_SFR 7:4
ENMON 3
RESERVED 2:1
REFOK 0
R/W/C Default
RW 0x0
R/W/C
RW
RW
RO
RW
0x0
0x1
0x0
Default
0x0
Reserved
Description
Description
Turn on Monitor function by default
Reserved
If 1'b1, will force the refok pin to 1, otherwise, it is control by the RTC/oscok
EOS S3 TRM (r1.01a) Confidential Page 146
0x090
Table 17-14: OSC_CTRL_4 Register
OSC_CTRL_4
Bit Field
RESERVED
WR
CE
TEST
31:0 bit
31:6
5
4:3
2:0
Table 17-15: OSC_CTRL_5 Register
0x094 OSC_CTRL_5
Bit Field
RESERVED
SDI
31:0 bit
31:1
0
Table 17-16: OSC_CTRL_6 Register
0x098 OSC_CTRL_6
Bit Field
RESERVED
SCK
31:0 bit
31:1
0
Table 17-17: OSC_STA_0 Register
0x0A0 OSC_STA_0
Bit Field
RESERVED
ANATESTREQ
31:0 bit
31:2
1
R/W/C
RW
RW
RW
Default
0x0
0x0
0x0
R/W/C
RW 0x0
Default
R/W/C
RW 0x0
Default
R/W/C
RHW 0x0
Default
LOCK 0 RHW 0x0
Table 17-18: OSC_STA_1 Register
0x0A4 OSC_STA_1
Bit Field
RESERVED
31:0 bit
31:1
SDO 0
R/W/C Default
RHW 0x0
Table 17-19: APC_CTRL_0 Register
The Analog Power Controller group is part of the PMU
0x100 APC_CTRL_0
Bit Field
RESERVED
DIS
31:0 bit
31:1
0
R/W/C
RO 0x0
Default
Description
Please refer OSC datasheet for detail
Please refer OSC datasheet for detail
Please refer OSC datasheet for detail
Description
Please refer OSC datasheet for detail
Description
Please refer OSC datasheet for detail
Description
Please refer OSC datasheet for detail, NO SYNC, FW needs to read it twice to ensure the value.
Please refer OSC datasheet for detail, NO SYNC, FW needs to read it twice to ensure the value.
Description
Please refer OSC datasheet for detail, NO SYNC, FW needs to read it twice to ensure the value.
1'b0 : APC ON, Always ON
Description
EOS S3 TRM (r1.01a) Confidential Page 147
Table 17-20: APC_CTRL_1 Register
0x104 APC_CTRL_1
Bit Field
RESERVED
31:0 bit
31:8
VT 7:3
R/W/C Default
RW 0x00
Description
Please refer OSC datasheet for others
(No SYNC Needed)
Please refer OSC datasheet for others
(No SYNC Needed)
TT 2:0
Table 17-21: APC_CTRL_2 Register
0x108 APC_CTRL_2
Bit Field
RESERVED
31:0 bit
31:7
TEST 6:3
RW 0x00
R/W/C Default
RW 0x0
Description
Please refer OSC datasheet for others
(No SYNC Needed)
Please refer OSC datasheet for others
(No SYNC Needed)
IT 2:0
Table 17-22: APC_STA_0 Register
0x120 APC_STA_0
Bit Field
RESERVED
TESTREQ
31:0 bit
31:5
4
RW 0x0
R/W/C
RHW 0x0
Default
DIGTESTBUS 3 RHW 0x0
Description
Please refer APC datasheet for detail, NO SYNC, FW needs to read it twice to ensure the value.
Please refer APC datasheet for detail, NO SYNC, FW needs to read it twice to ensure the value.
Please refer APC datasheet for detail, NO SYNC, FW needs to read it twice to ensure the value.
Reserved
PORZ
RESERVED
2
1:0
Table 17-23: RING_OSC Register
0x180 RING_OSC 31:0
Bit Field
RESERVED bit
31:8
GENERAL_PURPOS_SFR 7:1
RING_OSC_EN 0
RHW
RO
0x1
0x0
R/W/C
RW
Default
0x00
RW 0x0
Description
1'b1: Turn on the RING OSC, Ring OSC will be always on despite the HW control.
EOS S3 TRM (r1.01a) Confidential Page 148
Table 17-24: LDO_30_CTRL_0 Register
0x200 LDO_30_CTRL_0
Bit Field
RESERVED
31:0 bit
31:10
R/W/C Default
LDO_30_DI
LDO_30_IMAX
LDO_30_DISPG
9:5
4:2
1
RW
RW
RW
0x11
0x3
0x0
Description
Reserved
Output voltage programming
DI Vo (V)
00000 0.75
00001 0.77
00010 0.79
00011 0.81
00100 0.83
00101 0.85
00110 0.87
00111 0.89
01000 0.91
01001 0.93
01010 0.95
01011 0.97
01100 0.99
01101 1.01
01110 1.03
01111 1.05
10000 1.07
10001 1.09
10010 1.11
10011 1.13
10100 1.15
10101 1.17
10110 1.19
10111 1.21
Configures the control for maximum expected current imax current (mA)
000 1
001 2
010 4
011 8
100 12
101 16
110 22
111 30
It is used to disable the power good comparator.
1'b0 : Enable
1'b1 : Disable (the pg output is forced to “1”)
Used to disable LDO
1'b0 : Enable
1'b1 : Disable
LDO_30_DIS 0 RW 0x0
Table 17-25: LDO_30_CTRL_1 Register
0x204 LDO_30_CTRL_1
Bit Field
RESERVED
LDO_30_TESTREQ
31:0 bit
31:5
4
R/W/C
RO 0x0
Default
LDO_30_TEST 3:0 RW 0x0
Description
Reserved
Request of connection of the ANATESTBUS to an external pin for characterization - Reserved
Lab test and internal block characterization test control pins -
Reserved
EOS S3 TRM (r1.01a) Confidential Page 149
Table 17-26: LDO_50_CTRL_0 Register
0x210 LDO_50_CTRL_0
Bit Field
RESERVED
31:0 bit
31:10
R/W/C Default
LDO_50_DI
LDO_50_IMAX
LDO_50_DISPG
9:5
4:2
1
RW
RW
RW
0x11
0x3
0x0
Description
Reserved
Output voltage programming
DI Vo (V)
00000 0.75
00001 0.77
00010 0.79
00011 0.81
00100 0.83
00101 0.85
00110 0.87
00111 0.89
01000 0.91
01001 0.93
01010 0.95
01011 0.97
01100 0.99
01101 1.01
01110 1.03
01111 1.05
10000 1.07
10001 1.09
10010 1.11
10011 1.13
10100 1.15
10101 1.17
10110 1.19
10111 1.21
Configures the control for maximum expected current imax current (mA)
000 1
001 2
010 4
011 8
100 12
101 20
110 30
111 50
It is used to disable the power good comparator.
1'b0 : Enable
1'b1 : Disable (the pg output is forced to “1”)
Used to disable LDO
1'b0 : Enable
1'b1 : Disable
LDO_50_DIS 0 RW 0x0
Table 17-27: LDO_50_CTRL_1 Register
0x214 LDO_50_CTRL_1
Bit Field
RESERVED
LDO_50_TESTREQ
31:0 bit
31:5
4
R/W/C
RO 0x0
Default
LDO_50_TEST 3:0 RW 0x0
Description
Reserved
Request of connection of the ANATESTBUS to an external pin for characterization - Reserved
Lab test and internal block characterization test control pins -
Reserved
EOS S3 TRM (r1.01a) Confidential Page 150
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