A.2.

Structure of a register definition

The following table is a typical register description. The first column of the heading is the address offset within the module. Second column of the heading is the register name, while body is bit field name, Third column of the heading is the bit width of the register (typically 32-bit or [31:0]), while body is bit number(s) of the bit field. Fourth column indicates whether the register can be read (R) or written (W) by M4. More details below. Fifth column is the default value after reset.

Table: Sample Register bit Definition

0x030

Power_Down_

Scheme

Bit Field Bit R/W/C Default Description

RESERVED 31:8 RO –

M4M4S0_PD

…

SRAM_PD

…

M4M4S0_WU

…

SRAM_WU

7

6

5

4

3

2

1

RW

RW

RW

RW

0x0

0x0

0x0

0x0

Reserved

1’b1: If M4 and M4S0 PD event happen at same time, then M4 and M4S0 will put into power saving mode at same time

…

1’b: If more than one SRAM (M4S1 –

M4S15, NOT include M4S0) PD event happens at same time, these SRAMs will power down in parallel.

1'b0: If more than one SRAM (M4S1 –

M4S15) PD event happens at same time, these SRAMs will power down in the following priority.

M4S1→M4S2→…→M4S14→ M4S15 (M4S1 has the highest priority and M4S15 has the lowest priority)

…

1’b1: If M4 and M4S0 WU events happen at same time, then M4 and M4S0 will wake up at same time

…

1’b1: If more than one SRAM(M4S1 –

M4S15, NOT include M4S0) WU events happen at same time, these SRAMs will wake up in parallel.

1'b0: If more than one SRAM (M4S1 –

M4S15) WU event happens at same time, these SRAMs will wake up in the following priority. M4S1→M4S2→…→M4S14→

M4S15 (M4S1 has the highest priority and

M4S15 has the lowest priority)

EOS S3 TRM (r1.01a) Confidential Page 361

Table: Read/Write/Clear definitions

R/W/C Definition

RW

RO

Read / Write

Reserved bit

M4 read returns value previously written this bit is reserved or undefined

M4 write

Control or Data bit

Hardware

Uses the value

RO

RHW

Read Only

Read / Hardware

Write

Status or value bit

Status or value bit

No effect or must always write 0

No effect or must always write 0

No effect or must always write 0

Reserved / Undefined

Value set by hardware

Value set by hardware

RWHC

RW1C

Read / Write /

Hardware Clear

Read / Write 1 to Clear

Control bit returns value previously written, or may be cleared after an hardware event

Status / flag bit; typically 0 means default state or flag is not set (event has not occurred)

Control bit

Writing 0 has no effect

Writing 1 will clear flag

M4 writing 1 will initiate hardware event which will clear this bit after event is done.

Value is reflects hardware status/flag

M4 writing 1 will clear the flag

RW1S

Read / Write 1 to Set

Status / flag bit; typically 0 means default state

Writing 0 has no effect

Writing 1 will set flag or control

Control bit

Value is reflects hardware status/flag

M4 writing 1 will set the flag

Uses the value WO Write Only

Number representation:

Undefined

2'b11 = 2 bit binary number (decimal equivalent is 3)

4'hf = 4 bit hexadecimal number (decimal equivalent is 15)

0x0FF = 3 nibble hexadecimal number (decimal equivalent is 255)

31:0 = 31 down to 1, typically represents bit index.

EOS S3 TRM (r1.01a) Confidential Page 362