SPI Master. Qwiic QuickLogic Thing Plus - EOS S3

34.1

SPI Master

Here is a high-level block diagram for the SPI Master. Please refer to Figure below.

Figure 34-1: SPI Master Block Diagram

Programming the SPI Master go through the APB bus interface. There is a register block inside the SPI Master.

The SPI master can both transmit serial data and receive serial data from SPI slaves. The width of the transmit FIFO and receive FIFOs are 16-bits wide. Transmit FIFO is 131 entries deep. Receive FIFO is 8 entries deep.

Writing SPI_DR0 (0x060) register will push data transmit FIFO. Reading SPI_DR0 register will pop data from the receive FIFO. Use the status bits in SPI_SR register to see when Transmit FIFO is empty (TFE) or when the

Receive FIFO is full (RFF). Interrupts can be triggered on these status bits as well.

The SPI_BAUDR register controls the SPI clock to the SPI Slaves. It is recommended that SPI clock be ½ of the

C02 clock frequency. Write 0x2 or higher multiples of 2 to SPI_BAUDR.

34.2

SPI Transfer Modes

The transfer mode (TMOD) is set by writing control register SPI_CTRL0.

EOS S3 TRM (r1.01a) Confidential Page 314