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25.5
SPI_0_Master Registers
25.5.1
Address Map
The table below shows the memory map of the SPI register set. There are eight registers that control the SPI operation.
The address listed for each register is the offset from the base address of the chip select of the processor.
Table 25-1: SPI_0_Master register address table
Description Address Access Reset
Value
0x00
0x01
RW
RW
0x01
0x00
0x02
0x03
0x03
RW
W
R
0x00
0x00
0x00
0x04
0x04
0x05
W
R
RW
0x00
0x00
0x00
SPI Baud Register, Divisor LSB
SPI Baud Register, Divisor MSB
SPI Configuration Register
Transmit Register
Receive Register
Command Register (SPI Transfer Register)
Status Register
Slave Select Register
0x06 RW 0x07 SPI bit / serial clock control
0x07 RW 0x00
25.5.2
Register Descriptions
Additional serial clock cycles required after CSn de-activated
This section provides a detailed description of all the registers in the SPI Host Controller and the corresponding bits.
25.5.2.1
Register: SPI Baud Register LSB (SPIBR LSB) (Offset 0x00)
This is a Read/Write register and it controls the baud rate of the SPI system.
Bits
7:0
Type
R/W
Default Description
0x01
Divisor register LSB
25.5.2.2
Register: SPI Baud Register MSB (SPIBR MSB) (Offset 0x01)
This is a Read/Write register and it controls the baud rate of the SPI system.
Bits
7:0
Type
R/W
Default Description
0x00
Divisor register LSB
EOS S3 TRM (r1.01a) Confidential Page 245
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