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25.6
Programming
25.6.1
SPI Host Operation
This section describes the configuration and operation of the SPI Host Controller and details how the reads and writes are performed with the external slave device.
25.6.2
Read Operation
To perform a master read operation:
1.
Program the Divisor register (SPIBR, Offset Address 0x00 & 0x01, 2 Bytes) for setting up the required baud rate bits.
2.
Set up the SPI controller by writing to the SPI configuration register (offset 0x02).
Note: Steps a through e can be performed with a single write to address offset 0x02 a.
Enable the SPI by setting the SPE bit (bit [7]) to “1” b.
Configure the shift-out direction by setting the LSBFE bit ( bit [0])
If data is to be transferred least significant bit (LSB) first, set LSBFE to ‘1’
If data is to be transferred most significant bit (MSB) first, set LSBFE to ‘0’ c.
Set the SPI clock phase (CPHA, bit [2]) and polarity bits (CPOL, bit [3]) to the desired setting d.
Enable the SPI interrupts by setting the SPIE bit (bit [6]) to “1”
3.
Select an external slave by asserting the corresponding bit in the Slave Select Register (offset 0x05). For example, to select the slave device connected to the SS_bar [7], set the S7 bit (bit [7]) to “1”.
4.
Write to the Transmit register (offset 0x03) with the desired address.
5.
Start address transfer by writing to the SPI Command/ Transfer Register (offset 0x04)
Note: Steps a and b can be performed with a single write (0x05) to address offset 0x04
6.
After the address byte transaction is complete the SPI controller generates an interrupt signal, IW (offset
0x04, bit 1).
Note: This interrupt signal automatically clears the Start bit (Command register, bit [0]) to “0”.
To acknowledge and clear the interrupt, the processor must write to the IACK bit (bit[7]) in the command register (offset 0x04)
Also, TIP_o output (Status register, bit [2]) can be monitored to see if SPI transaction is complete
7.
Start SPI read transaction by writing to the SPI Command/ Transfer Register (offset 0x04).
Note: Steps a and b can be performed with a single write (0x09) to address offset 0x04 a.
For a read operation, set the Write bit (bit [2]) to “0” and the Read bit (bit [3]) to “1”. b.
To start the read process, set the Start bit (bit [0]) to “1”.
8.
After the first byte read transaction is completed the SPI controller generates an interrupt signal to the processor, IR (offset 0x04, bit 0).
Note: This interrupt signal automatically clears the Start bit (Command register, bit [0]) to “0”.
To acknowledge and clear the interrupt, the processor must write to the IACK bit (bit[7]) in the command register (offset 0x04)
9.
If more bytes need to be read, steps 7 and 8 are repeated.
10.
Once the desired numbers of data bytes have been read, to complete the whole SPI transaction write 1 to
Stop bit (bit][1]) of the SPI Command/ Transfer Register. This will make the corresponding SPI_CSn line to de-activate (SPI_CSn goes high)
EOS S3 TRM (r1.01a) Confidential Page 251
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